Hitachi, Ltd.

Other

Renesas Technology Corp.

Hitachi Device Engineering Co., Ltd.

Takahide Ikeda

Atsuo Watanabe

Mitsuru Hirao

Yoichi Tamaki

Toshiyuki Kikuchi

Nobuo Tanba

Kiyoo Itoh

Takao Watanabe

Yutaka Kobayashi

Ryoichi Hori

Goro Kitsukawa

Katsuhiro Shimohigashi

Noriyuki Homma

Hideaki Uchida

Shinji Nakazato

Masahiro Yamamura

Takashi Kobayashi

Takeo Shiba

Atsushi Hiraishi

Tatsuya Kamei

Hiromi Shimamoto

Kazuhiro Ohnishi

Yoshikazu Saito

Takashi Uchino

Touji Mukai

Kiyoshi Tsukuda

Katsumi Ogiue

Masanori Odaka

Nobuo Tamba

Osamu Saito

Takahiro Nagano

Hiroo Masuda

Shinichiro Mitani

Yoshiaki Yazawa

Naohiro Momma

Akira Fukami

Masayuki Ohayashi

Kouichirou Yamada

Tadashi Kuramoto

Asao Nishimura

Hideo Miura

Takashi Hashimoto

Hiroyuki Ohta

Masataka Minami

Kazutaka Mori

Hisayuki Higuchi

Kazuo Tanaka

Ryuichi Saito

Takeshi Tokuyama

Isao Yoshida

Yasuo Wada

Nobuyoshi Natsuaki

Nobuaki Miyakawa

Shigeru Nishimatsu

Satoru Isomura

Masao Tamura

Toshiro Hiramoto

Masami Usami

Toru Koizumi

Toji Mukai

Michio Ishikawa

Katsumi Tsuneno

Kimiko Aoyama

Hisako Sato

Takahide Nakamura

Osamu Saitoo

Ryuichi Saitoo

Yoshikasu Saito

The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

Semiconductor device and process of producing the same

Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

Semiconductor memory device

A semiconductor device having a field effect transistor formed in a semiconductor layer provided on an insulating layer is provided with a body electrode electrically connected to a channel forming region of the field effect transistor, and a back gate electrode provided below the insulating layer so as to be opposed to the channel forming region of the field effect transistor. A potential for controlling carriers of conduction type opposite to a channel formed in an upper portion of the channel forming region of the field effect transistor is applied to each of the body electrode and the back gate electrode. Thus, the withstand voltage for the drain of the field effect transistor can be increased. It is also possible to stabilize the threshold voltage of the field effect transistor. Furthermore, the threshold voltage of the field effect transistor can be changed in a stable state.

Semiconductor device

The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the polycrystalline first silicon layer has a positive in temperature dependence of resist while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistances while the second polycrystalline layer has a negative temperature dependance of resistance, or vise versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

A method of fabricating a semiconductor device is provided wherein a first semiconductor substrate is prepared with a first insulating film formed over a first main surface of the first semiconductor substrate, s semiconductor film of n-type conductivity formed over the first insulating film, and a second insulating film formed over the semiconductor film so as to cover the first main surface. A second semiconductor substrate is also prepared with a third insulating film formed over the second semiconductor substrate. Next, the second insulating film and third insulating films are bonded together by thermal processing to join the first semiconductor substrate and the second semiconductor substrate. A portion of a second main surface of said first semiconductor substrate, opposite to said first main surface of the first semiconductor substrate is then removed to expose a portion of the first semiconductor substrate, thereby providing a semiconductor layer. A gate insulating film for an MISFET is formed over the semiconductor layer; a gate electrode for the MISFET is formed over the gate insulating film, and source and drain region for the MISFET are formed in the semiconductor layer. With this arrangement, the first insulating film serves as a gate insulating film for the MISFET, and the semiconductor film serves as a gate electrode for the MISFET.

Method of manufacturing an improved SOI (silicon-on-insulator)

Semiconductor device having conducting structure

A semiconductor device has a well region formed in the surface of a substrate, and has functional portions such as MOSFET and bipolar transistor formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.

Semiconductor device having semiconductor elements formed in a

An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

Bimos semiconductor integrated circuit device including high speed

A semiconductor integrated circuit device includes an element separating first and second grooves formed to surround active regions to be formed with a semiconductor element. In addition a third groove is formed to surround at least a portion of the first groove, when viewed from a plane view. In the semiconductor integrated circuit device, the active regions and an element separating region of a silicon layer are insulated from each other by the separating grooves extending from the main surface of the silicon layer to an underlying insulating layer, and are fed with a common fixed potential.

Semiconductor integrated circuit device including an improved separating

Growing community of inventors

Tokorozawa, Japan

Takahide Ikeda