Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Takahide Baba

Daisuke Murakami

Yuji Takai

Yoshiharu Watanabe

Isao Kawamoto

Toshihiro Fukuyama

Seiji Horii

Tetsuji Kishi

Yuki Soga

Yasuo Nishioka

Provided is a memory interface circuit connected to a memory device that outputs a first data signal, and including: a first delay unit delaying a first strobe signal outputted from the memory device by a first delay amount to generate a first delayed strobe signal; a first data latch unit latching the first data signal as a first latched data signal in synchronization with the first delayed strobe signal; a first range calculating unit calculating a first delay range width that is a width of a range of values of the first delay amount which allow the first data latch unit to correctly latch the first data signal as the first latched data signal; and a drive capability setting unit adjusting the drive capability of the memory device so as to widen the first delay range width.

Memory interface circuit and drive capability adjustment method for memory device

A clock enable (CKE) control circuit () is provided between a memory control circuit () and a SDRAM (). When a system is in, e.g., a sleep state, the CKE control circuit () controls a CKE signal outputted to the SDRAM () such that it is fixed to a Low level. As a result, it is possible to halt a power supply provided to the memory control circuit (), while maintaining the low-power-consumption mode of the SDRAM (), so that power consumption resulting from a leakage current is suppressed. In addition, it becomes also possible to reset the memory control circuit (), while maintaining the low-power-consumption mode of the SDRAM ().

Memory control device

A transmission cancellation section is provided on a bus connecting a master and a slave. During a reset of the master, the transmission cancellation section blocks the bus so that an invalid command flowing on the bus does not reach the slave and executes, instead of the master stopped by the reset operation, generation of data which corresponds to an access request command already output to the slave and is to be sent to the slave and receiving of data from the slave.

System and method for bus transmission cancellation

Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.

Resource management device

A resource management device of the present invention, used in a system where at least one bus master is connected to each of a plurality of buses, includes: a bus arbitration section for arbitrating an amount of access to be made from the buses to a shared resource; an arbitration information management section for managing, as bus arbitration information, a bus priority order and a highest access priority pattern for ensuring a predetermined access bandwidth to the shared resource for each bus for an arbitration operation by the bus arbitration section; and a resource control section for controlling, based on characteristics of the shared resource, an access to the shared resource from the bus whose access request has been granted by the bus arbitration section. Thus, it is possible to guarantee a minimum bandwidth for access to the shared resource for each of the plurality of bus masters.

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Hyogo, Japan

Takahide Baba