Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Takaharu Yoshida

Osamu Shibata

Masayuki Toyama

Hiroshi Suenaga

Keisuke Sakai

Toru Iwata

Yoshiyuki Saito

Noriaki Takeda

Masahiro Nakamura

Atsushi Shinkai

Yutaka Taguchi

Hiroshi Sakurai

Chie Sasaki

A signal transmission device includes a differential driver, a first single-ended driver circuit block, a second single-ended driver circuit block, a control circuit, and a common-mode filter. In the case where two-channel single-ended transmission is performed by using the first and second single-ended driver circuit blocks, the control circuit controls a driving capability of the first single-ended driver circuit block and a driving capability of the second single-ended driver circuit block in accordance with a combination of a change in a logical value of an output signal of the first single-ended driver circuit block and a change in a logical value of an output signal of the second single-ended driver circuit block.

Signal transmission device, signal transmission system, signal transmission method, and computer device

A communication system in which an operating voltage can be selected from a plurality of interface voltages enables an interface voltage to be switched in a stable manner during operation of the system. When the interface voltage is to be switched, a host device () and a slave device () perform the switching while maintaining the signal level of buses in a stable manner. This structure enables the communication system to switch an interface voltage using a small number of signal lines.

Interface device for host device, interface device for slave device, host device, slave device, communication system and interface voltage switching method

It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal. The invention provides a signal transmission method that is characterized in that a reception side and a transmission side partition data into a plurality of data fragments and send and receive the plurality of data fragments over at least two transmission lines, in that the transmission side transmits first data fragments of the plurality of data fragments over a first transmission line of the transmission lines, transmits data packets that include header information, a second data fragment that has the same bit length as the first data fragments, and footer information over a second transmission line other than the first transmission line, and transmits the first data fragments and the second data fragments in synchronization, and in that an interrupt signal for controlling the transmission side is transmitted from the reception side to the transmission side in a time slot that is an interval between first data fragments that are adjacent on the first transmission line.

Method, device, and system for transmitting data fragments over multiple transmission lines and techniques for stopping data transmission

An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section that receives a transmission/reception clock, which is used for transmitting/receiving data between the host terminal and the removable memory device, from the host terminal; a phase synchronization pattern generation section that generates a phase synchronization pattern, which is for adjusting a phase of internal reception clock which the host terminal incorporates for receiving data from the removable memory device, based on the transmission/reception clock; and a transmission section that transmits the generated phase synchronization pattern to the host terminal, and in which the phase synchronization pattern includes a first level signal which lasts for at least two cycles, and a second level signal which follows the first level signal and lasts for one cycle, is provided.

Removable memory device, phase synchronizing method, phase synchronizing program, medium recording the same, and host terminal

An adapter for a memory device for connecting a detachable memory device to an AT attachment (ATA) interface of a host computer and a connecting method using the adapter are presented. With a conventional adapter which is not supplied with a number of heads and a number of sectors per track of the memory device in advance, the actual numbers of the memory area of the memory device may be different from those supplied the adapter for a memory device. This prevents the memory device from being normally accessed in a cylinder head sector (CHS) mode by the adapter. The adapter for a memory device according to the present invention identifies a file format of data stored in the memory area in the memory device, and retrieves and saves data about the number of heads and the number of sectors per track. Even if the adapter is not previously supplied with the number of heads and the number of sectors per track of the memory device, it accordingly allows the memory device to be accessed in the CHS mode.

Adapter for memory device and connecting method using the same

Growing community of inventors

Osaka, Japan

Takaharu Yoshida