Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Other

Renesas Electronics Corporation

Mitsubishi Electric Engineering Company, Limited

Takaharu Tsuji

Tsukasa Ooishi

Hideto Hidaka

Hiroaki Tanizaki

Masatoshi Ishikawa

Hiroshi Kato

Shigeki Tomishima

Mikio Asakura

Tadaaki Yamauchi

Mitsutaka Niiro

Yasumitsu Murai

Masanao Maruta

Kyoji Yamasaki

Koji Tanaka

Hiroki Shimano

Shuichi Ueno

Toshiaki Kawasaki

Akinori Shibayama

Takashi Ito

Genta Watanabe

Masanori Hayashikoshi

A semiconductor device having first and second digit line drivers and a bit line driver. When the address of one segment has been input from the outside, a segment decoder selects one segment corresponding to the address and couples the same to the selected first digit line driver. When the addresses of two or more segments have been input from the outside, the segment decoder selects two or more segments corresponding to the addresses and couples the selected two or more segments to the respective digital line drivers.

Semiconductor device

A write disturbance margin of reference cells that generate reference current during read is improved. A bit line forms a clad interconnect structure in the normal cell region where normal cells are disposed, and a partially clad or non-clad interconnect structure in the reference cell region where a reference cell is disposed. Thus, a writing magnetic field intensity applied to the reference cell is smaller than the write magnetic field intensity applied to a normal memory cell during identical write currents.

A magnetic memory device is provided in which, even when a recording layer having an asymmetric shape and a local via are formed over a strap wiring with a sufficient distance allowed therebetween, increase in the size of the magnetic memory device can be suppressed. The magnetic memory device includes the strap wiring, the local via, and a magnetic recording element (TMR element). The TMR element includes a fixed layer and the recording layer. The planar shape of the recording layer is asymmetric with respect to the direction of the easy magnetization axis of the recording layer and is symmetric with respect to the axis of symmetry perpendicular to the easy magnetization axis. The contoured portion of the recording layer on the side closer to the center of area of the recording layer is opposed to the local via formation side.

Magnetic memory device

Magnetic memory devices integrated together with a logic circuit on a common semiconductor chip are arranged to have layouts mirror-symmetrical (mirror inversion) with respect to an axis parallel to a magnetization-hard axis of a magneto-resistance element of a magnetic memory cell in the magnetic memory device. The logic circuit is arranged between the magnetic memory devices. The magnetic memory device capable accurately of maintaining integrity in logical level between write data and read data is achieved.

Semiconductor integrated circuit device and magnetic memory device capable of maintaining data integrity

A semiconductor integrated circuit device includes a plurality of memory cells storing data; a write current line arranged near the memory cells or electrically connected to the memory cells; a first constant current generating circuit providing an output current having a temperature dependence; a second constant current generating circuit providing an output current having a temperature dependence different from that of the output current of the first constant current generating circuit; a mixing circuit mixing the output currents of the constant current generating circuits together to provide a composite current at a variable mixing rate; and a write current electrically connected to the write current line and writing data into the memory cell by passing a write circuit through the write current line based on the composite current provided by the mixing circuit.

Semiconductor integrated circuit device with a plurality of memory cells storing data

Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.

Nonvolatile semiconductor memory device

Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.

Thin film magnetic memory device provided with a dummy cell for data read reference

A terminating circuit for terminating a common data bus to a predetermined voltage level is inactivated in a test mode, a level detection circuit detects a potential of an internal test data bus line coupled to the common data bus line, and an output state of a ternary output circuit is controlled in accordance with a detection result. In a semiconductor integrated circuit device including the memory integrated together with a logic on a common semiconductor substrate, it is accurately determined whether the output state of the memory is a ternary state while operating the memory under actual operation conditions.

Tester built-in semiconductor integrated circuit device

In a shift switch circuit for replacing a data line, a transmission gate circuit connecting node N2 corresponding to ith write data line to node N4 corresponding to ith read data line is provided. An operation of the shift switch circuit can be confirmed according to whether or not an output corresponding to provided data input signal D&#x3c;i&#x3e; is observed as data output signal Q&#x3c;i&#x3e;. Preferably, a transmission gate connecting i+1th write data line to an output data line is further provided, in order to further ensure operation confirmation. When a fuse circuit is set to replace a data line, ratio of successful chip repairing will be higher.

Semiconductor memory device capable of testing data line redundancy replacement circuit

Each of N memory blocks of first to Nstages includes a plurality of first and second driver units. The plurality of first and second driver units are respectively provided corresponding to one end and another end of a plurality of digit lines included in each memory block. Each of the first driver units in memory blocks before a selected memory block connects a corresponding digit line to a first voltage according to a voltage level on a digit line of the same row in a memory block of a previous stage. A second driver unit in the selected memory block connects a corresponding digit line to a second voltage in order to supply a data write current. In other words, digit lines in the memory blocks before the selected memory block are not used as current lines but as signal lines.

Thin film magnetic memory device for selectively supplying a desired data write current to a plurality of memory blocks

In a normal data reading, one of word lines and one of first and second dummy word lines are selected and data is read out through the access to selected regular memory cell and a reference cell. In a test mode, each of word lines are turned to a non-select state and both of first and second dummy word lines are selected and by setting one of first and second reference voltages to a level different from a level during the normal data reading, data is read out through the access to the reference cells.

Magnetic memory device with reference cell for data reading

An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.

Semiconductor integrated circuit device with internal power supply potential generation circuit

A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

Semiconductor device with reduced current consumption in standby state

A dummy cell has a plurality of dummy magneto-resistance elements which have the same characteristic as a magneto-resistance element, which characteristic changes corresponding to a voltage applied to the opposite ends. In addition, a voltage applied to opposite ends of each dummy magneto-resistance element is made smaller than a voltage applied to opposite ends of a magneto-resistance element of a memory cell. With this, the dummy cell is designed so as to have an intermediate electric resistance between first and second electric resistances.

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Hyogo, Japan

Takaharu Tsuji