Fujitsu Corporation

Fijitsu Limited

Takaharu Ishizuka

Takashi Yamamoto

Toshikazu Ueki

Takeshi Owaki

Makoto Hataida

Yuka Hosokawa

Daisuke Itou

Atsushi Morosawa

Takao Matsui

Susumu Akiu

Seishi Okada

Takumi Takeno

Fumitake Sugano

Takato Noda

Katsunori Takeshita

Daisuke Itoh

Yasuhide Shibata

Atsushi Morozawa

A transmission/reception device includes a transmission device that divides a plurality of connection lines into a plurality of groups, determines corresponding connection lines in the plurality of groups, determines a correspondence between test pattern and the connection line, and outputs the test pattern to the plurality of connection lines based on the correspondence between the test pattern and the connection line, and a reception device that receives the test pattern from the transmission device, compares bits in a same position of the test pattern received through a corresponding connection line in the plurality of groups based on the correspondence between the test pattern and the connection line, and generates erroneous connection line information indicating an erroneous connection line as a connection line in which an error has occurred in the plurality of connection lines based on a result of the comparison.

Transmission/reception device, transmission device, reception device, and data transmission/reception method

To prevent a decrease in performance of controlling a snoop tag. A queue is stored with REPLACE target WAY information and an index as an entry associated with a REPLACE request received from a processor, the index stored in the queue is compared with an index of a subsequent READ request, and, as a result of the comparison, a process based on the index-coincident READ request is executed with respect to the snoop tag corresponding to a content of a cache memory of the processor. Further, the REPLACE target WAY information of the READ request is replaced with the WAY information in the index-coincident entry within the queue.

Control device for snoop tag

A verification device includes a data verifying unit that verifies whether data in a packet has an error using a first or a second verification mode, a packet generating unit that generates a packet in accordance with a first packet generation mode or a second packet generation mode respectively corresponding to the first and the second verification modes, a failure monitoring unit that monitors a failure of a transmission line that requires a switching of the verification mode, a switching packet transmitting unit that transmits to a destination device, a switching packet for informing the switching of the verification mode used by the data verifying unit when the failure monitoring unit detects a failure or a removal of a failure, a generation mode switching unit that switches the generation mode, and a verification mode switching unit that switches the verification mode to the one informed by the switching packet.

Verification device, verification method, and verification program

A method of updating a routing table includes: receiving, from an issue-source node, a write packet that includes update data for updating the routing table; attempting to recognize, based upon contents of the write packet, a partition in which the issue-source node is included; determining whether to permit updating the routing table based upon (1) whether the partition including the source node is recognized and (2) whether port information and partition information in the update data are stored in the routing table; and updating the routing table when updating is permitted.

Method of updating routing table, data transfer apparatus, and program

A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in a firmware hub instructs the northbridge to inhibit an external instruction. In addition, the firmware saves the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU saved on the memory to all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.

Information processing apparatus for inhibiting instructions, saving and restoring internal information in response to abnormality in redundant processor system

A request issued by the CPU is output from the local arbiter by way of the CPU bus and the CPU-issued request queue. The cache replacement request loop-back circuit determines at the loop-back determination circuit whether the outputted request is a cache replacement request or not. A request other than a cache replacement request is output onto the local bus. A cache replacement request is output to the selector and sent to the request handling section when there is no valid request on the global bus.

Multiprocessor system, system board, and cache replacement request handling method

An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.

Information processing device and error processing method

A control device managing a plurality of nodes transmitting and receiving data containing an error correcting code, comprises means accepting, when any one of the nodes detects an uncorrectable error from the data containing the error correcting code, a signal transmitted by the node detecting the error, means judging from a record of the detection of a first node, when accepting the signal from a second node receiving data transmitted by the first node, whether or not the first node has detected the uncorrectable error from the data transmitted to the second node, and means stopping, when the first node has detected the uncorrectable error from the data transmitted to the second node, a process attributed to the acceptance of the signal from the second node.

Node device, control device, control method and control program

In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest request other than a cache replace request is retained by an input-request retaining section. Consequently, even if an address of an issued request for cache replace request matches an address of a request retained by the CPU-issued request queue, the issued request for the cache replace request is not retried but is queued in the CPU-issued request queue when the address of the issued request for the cache replace request does not match the entire address retained by the input-request retaining section.

System controller, identical-address-request-queuing preventing method, and information processing apparatus having identical-address-request-queuing preventing function

In an information processing system loaded with a CPU having cache and a system controller having a copy of a tag of the cache (snoop tag), and the CPU not issuing replacement information about the cache tag, the number of WAYs of the snoop tags in the system controller is larger than the number of WAYs of the cache tags in the CPU to reduce a cache miss rate and suppress the degradation of performance by suppressing excess replacement of the cache tags in the CPU.

Information processing system, information processing board, and method of updating cache tag and snoop tag

A semiconductor integrated circuit includes a circuit block connected to an arithmetic processing unit via a bus, a power supply noise data generator which is configured to generate a power supply noise data signal by converting power supply noise generated in power supply voltage of power supply operates the circuit block, an error detector which is configured to detect an error of data outputted from the circuit block to the bus, and a write controller which is configured to associate power supply noise information based on the power supply noise data signal with data on the bus and write the data in a storage unit, and to stop to write the data in response to the detection of the error by the error detector.

Semiconductor integrated circuit, control method, and information processing apparatus

A cache-status maintaining unit stores address information of data stored in each entry of a cache memory, and maintains a status of each entry as any one of 'strongly modified', 'weakly modified', &#x201c;shared&#x201d;, and &#x201c;Invalid&#x201d;. A data-fetching-procedure selecting unit selects, upon receiving a data read request, at least one data fetching procedure based on the address information and the status. A read-data delivering unit selects latest data from among the data fetched, and delivers the latest data to a processor that issued the data read request. A cache-status updating unit updates, when registering the address information of the data, updates the status of the entry based on a type of the data read request.

Method and apparatus for controlling memory system

In a multiprocessor system, a system controller includes snoop tags which are copy information on cache tags retained by respective CPUs. If the same address is registered in S (Shared state) in the cache tag of each of the CPUs connected to the same CPU bus, the address is registered in S (Shared state) in only any one of the snoop tags corresponding to the CPUs in which the same address is registered.

System controller, snoop tag modification method and information processing apparatus having snoop tag modification function

An information processing device of a multiprocessor configuration that can increase significantly the processing capability of read requests. The information processing device comprises a plurality of processing units, a plurality of cache memories for storing temporarily the data read by the plurality of processing units from respective main memories in combination with tag information indicating the state of the data that will be stored, and a system controller for controlling the access of the plurality of processing units to the main memories. The system controller comprises a tag copy unit for holding a copy of the tag information that will be stored in the cache memory, a plurality of write cues for storing write requests, and a store buffer for storing the arbitration results relating to a plurality of write requests that will be stored in the plurality of write cues.

Information processing device and data control method in information processing device

A multiprocessor system includes a judging unit judging whether a read command inputted to a global address crossbar is a read command to a memory on an own system board, an executing unit speculatively executing, when the judging unit judges that the read command is a read command to the memory on the own system board, the read command before global access based on an address notified from the global address crossbar, a setting unit setting for queuing data read from the memory in a data queue provided on a CPU without queuing the data in a data queue provided on the memory, and an instructing unit instructing, based on notification from the global address crossbar, the data queue provided on the CPU to discard the data or transmit the data to the CPU.

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Kawasaki, Japan

Takaharu Ishizuka