Kabushiki Kaisha Toshiba

Takafumi Yamaji

Tetsuro Itakura

Shoji Otaka

Hiroshi Tanimoto

Osamu Watanabe

Takeshi Ueno

Hiroshi Yoshida

Masanori Furuta

Takashi Ueno

Daisuke Kurose

Akira Yasuda

Masahiro Hosoya

Akihide Sai

Yasuhiko Tanabe

Hiroshi Tsurumi

Hidenori Okuni

Junya Matsuno

Ryuichi Fujimoto

Tsutomu Sugawara

Hiroki Sakurai

Tadashi Arai

Nobuo Kanou

Shuichi Obayashi

Hiroki Shoki

Tsuneo Suzuki

Rui Ito

Yasushi Murakami

Yosuke Ogasawara

Tomohiko Ito

Tomohiko Sugimoto

Satoshi Arai

Naoya Waki

Hiroshi Horiguchi

Chikau Yakahashi

A radio apparatus includes a first receiver that is a processing unit for amplifying and frequency converting a radio signal received via an antenna, thereby outputting an IF signal; a detector unit for detecting a preamble signal from the IF signal; a second receiver for amplifying and quadrature demodulating the radio signal, thereby generating an I-signal and a Q-signal; a demodulator unit for demodulating the I-signal and Q-signal to generate a data signal; and a control unit for halting the operation of the first receiver and further activating the second receiver when the detector unit detects the preamble signal and for activating the first receiver and halting the operation of the second receiver when the demodulator unit completes the demodulation of the I-signal and Q-signal.

Radio apparatus

According to one embodiment, there is provided a fractional frequency dividing circuit including an integral frequency dividing circuit and an adjustment circuit. The integral frequency dividing circuit is configured to convert a reference signal to K (K is a positive integer) phase signals. Each of the K phase signals has a frequency of one nth (n is a positive integer) of the reference signal and has different phases from each other. The adjustment circuit is configured to weighting-add a plurality of signals corresponding to the K phase signals and generate a fractional-frequency-divided signal. The fractional-frequency-divided signal has a frequency of m times (m is a positive integer that is not multiplies of n) of each of the plurality of phase signals.

Fractional frequency dividing circuit and transmitter

According to one embodiment, there is provided a semiconductor device including a first amplifier and a second amplifier. The first amplifier has an input terminal to receive a first signal and an output terminal to output a second signal. The second amplifier is configured to receive the first signal and a correction data, to generate a correction signal according to the first signal and the correction data, and to output the generated correction signal to the output terminal of the first amplifier so as to add the first signal and the generated correction signal.

Semiconductor device and receiver

A radio apparatus includes an antenna; an amplifier that amplifies a radio signal, received via the antenna; a first mixer that frequency converts the amplified radio signal to generate a first analog signal; a first A/D converter that converts the first analog signal to generate a first digital signal; a second mixer that frequency converts the amplified signal to generate a second analog signal; a second A/D converter means that converts the second analog signal to generate a second digital signal; a demodulator means that demodulates the first and second digital signals to generate a demodulated signal; a detector that detects a preamble from the first digital signal; and a control means that halts the second mixer and second A/D converter during the wait for the radio signal and that activates the second mixer and second A/D converter when the detector detects the preamble.

A time error estimating device for estimating a sampling time error of each of a plurality of sampling circuits when the sampling circuits generates a plurality of sampling output signals by performing sampling at timings shifted from one another has correlators each configured to obtain a correlation value representing a similarity between the sampling output signals, and a weight adder configured to estimate the sampling time error of the sampling circuits, based on a result obtained by adjusting a weight on the correlation value.

Time error estimating device, error correction device and A/D converter

According to one embodiment, an analogue to digital converter converts an analogue input signal to a digital output signal. The converter includes an analogue to digital converting unit, a multiplexer, a pseudo-alias signal generator, a gain controller, and an alias signal compensator. The analogue to digital converting unit converts the analogue input signal to a plurality of digital signals. The multiplexer sequentially selects one of the digital signals and outputs the selected digital signal as a multiplexer output. The pseudo-alias signal generator generates a plurality of pseudo-alias signals from the digital signals. The pseudo-alias signal simulates an alias signal component in the multiplexer output. The gain controller generates a plurality of gain control signals by using the pseudo-alias signals. The gain control signal controls gain of the digital output signal. The alias signal compensator compensates the alias signal component by using the gain control signals.

Analogue to digital converter and signal processing system

An A/D converting apparatus includes a first A/D converter to sample an analog input signal having a D/A converter to generate a comparative signal for successive comparison with the analog input signal, a signal generator generate a differential signal between the analog input signal and the comparative signal, and a comparator to compare the comparative signal with a standard value to generate a first digital signal exhibiting high-order bit; an amplifier to amplify the differential signal to generate a residue signal; and a second A/D converter to sample the residue signal to generate a second digital signal exhibiting low-order bit.

A/D converting apparatus

According to an embodiment of the invention, there is provided a digital/analog converter includes: a decoder that converts a (n&#x2212;1)-phase input digital signal to a n-phase output digital signal; and a signal generating unit that generates analog signals according to the n-phase output digital signal.

Digital/analog converter and transmitter for complex signals

Disclosed is an AD converter including: a first conversion stage including a quantizing part to generate m parallel pieces of quantized signals from m pieces of input analog signals representing n-dimensional vectors (n&#x2266;m&#x2266;2n), a decoding part to generate m pieces of decoded analog signals from the m parallel pieces of quantized signals, and a residual amplifying part to output m pieces of amplified residual signals by multiplying respective differences between each of the m pieces of analog signals and each of the m pieces of decoded analog signals; a second conversion stage including a quantizing part to generate m parallel pieces of quantized signals from the m pieces of amplified residual signals; and a synthesizing part to generate m parallel pieces of digital signals by synthesizing each of the quantized signals in the first conversion stage and in the second conversion stage at each parallel position.

AD converter and radio receiver

An A/D converter which converts an analog current signal into a digital signal, includes: a filter removing a noise component from the analog current signal to output an analog voltage signal; a quantizer quantizing the analog voltage signal outputted from the filter to generate the digital signal; and a D/A converter converting the digital signal generated by the quantizer into an analog feedback current to feedback to an input of the filter, and supplying a bias current for the D/A converter to an output of a frequency converter via a path of the analog current signal as a bias current driving the frequency converter outputting the analog current signal.

A/D converter, signal processor, and receiving device

A D/A converter includes a plurality of current sources configured to be on or off according to input digital data; a constant voltage source configured to apply a constant voltage to the current sources; current supply wirings provided between the constant voltage source and the respective current source, the current supply wirings respectively having equal length from the constant voltage source to the respective current source; ground-side wirings summing up output currents from the plurality of current sources; and output terminals connected to the ground-side wirings, the output terminals outputting analogue data corresponding to the input digital data.

D/A converter and communication apparatus

A multiplier includes a first input terminal which receives a modulated signal, three second input terminals which receive first, second, and third local signals respectively, the first, second, and third local signals having a phase difference of 120&#xb0; from one another, a multiplication unit configured to multiply the modulated signal by each of the first, second, and third local signals, and output first, second, and third multiplied output signals, and three output terminals from which the first, second, and third multiplied output signals are derived, respectively.

Multiplier and radio communication apparatus using the same

An oscillator includes a plurality of oscillating units connected in parallel with each other, and a control unit which controls the number of parallel connections of the plurality of oscillating units based on an instruction signal indicating accuracy to be tolerated with respect to oscillation outputs of the oscillating units.

Parallel controlled connections of the plurality of ring oscillator units, PLL, radio apparatus

An amplifier includes an amplification unit which amplify a first difference between first and second input signals, a second difference between second and third input signals and a third difference between third and first input signals by a differential mode gain, and amplify an average of the first, second and third input signal by a common mode gain, for outputting a first output signal corresponding to a sum of the amplified first difference and the amplified average, a second output signal corresponding to a sum of the amplified second difference and the amplified average, and a third output signal corresponding to a sum of the amplified third difference and amplified average; first, second; and a reduction circuit which reduces the common mode gain less than the differential mode gain.

Amplifier, filter using the same, and radio communication device

Disclosed is an AD converter including: a first conversion stage including a quantizing part to generate m parallel pieces of quantized signals from m pieces of input analog signals representing n-dimensional vectors (n&#x3c;m&#x3c;2n), a decoding part to generate m pieces of decoded analog signals from the m parallel pieces of quantized signals, and a residual amplifying part to output m pieces of amplified residual signals by multiplying respective differences between each of the m pieces of analog signals and each of the m pieces of decoded analog signals; a second conversion stage including a quantizing part to generate m parallel pieces of quantized signals from the m pieces of amplified residual signals; and a synthesizing part to generate m parallel pieces of digital signals by synthesizing each of the quantized signals in the first conversion stage and in the second conversion stage at each parallel position.

Growing community of inventors

Yokohama, Japan

Takafumi Yamaji