Ando Electric Company

Takafumi Uehara

Junichi Saito

Haruhiko Fujii

Masayoshi Dehara

Kazuhiko Hirano

A timing adjusting circuit receives a clock and a data from an outside, and outputs the delayed data to the outside. A variable delay circuit receives the data and outputting the data delayed according to a value set by a delay value setting signal A first flip-flop has a data input terminal for inputting the data output from the variable delay circuit and a clock input terminal for receiving an inverse signal of the clock being frequency divided. A second flip-flop has a data input terminal for receiving a fixed value and a clock input terminal for receiving a signal output from the first flip-flop. A counter has a counter enable input terminal for inputting a signal output from the second flip-flop, counts the clock at every plural periods, and sends an output count value as the delay value setting signal to the variable delay circuit.

Timing adjusting circuit

A multirate generator for generating a rate signal and a multirate signal having a subrate period and a subrate number which are set for each period of the rate signal, which comprises a rate signal generation unit, a multirate signal generation unit, and a multirate number detection unit. The multirate generator operates the rate signal generation unit and the multirate generation unit by means of the same clock and makes the rate signal generation unit and the multirate generation unit generate, respectively, a rate signal and a multirate signal, to generate a rate signal and a multirate signal which have been timing-adjusted without delay elements and the like, and without requiring a timing adjustment. The rate data, multirate data and multirate number data may be optionally set, to enable outputting a desired rate signal and a desired multirate signal.

Multirate generator and multirate generating method

The object of the present invention is to offer a rate generator which is capable of generating rate signals of arbitrary time intervals over a wide range, from low speeds to high speeds. An N-bit (wherein N is a natural number) counter 1 counts up according to a clock signal 31. An adder 16 pairs off and adds consecutive rate data 32. An adder 17 pairs off and adds rate data 32 which has been shifted by a single step. An adder 18 sequentially adds the addition results of the adder 16. An adder 19 sequentially adds the addition results of the adder 17. A selector 4 alternately selects the addition results of the adder 18 and the addition results of the adder 19. A correspondence circuit 2 receives the output of the counter 1 as a first input and the output of the selector 4 as a second input, and detects matches between the two inputs. A pulse generation circuit 3 is inputted with the output of the correspondence circuit 2 and a clock signal 31, and outputs a rate signal 33.

Rate generator

A rate generating portion generates a second rate signal comprising a desired first rate signal having arbitrary time intervals preceded by a preceding rate signal composed of (N+1) pulses, a data row generating portion composed of N logic circuits and N D-type flip-flops generates an arbitrary data row with the second rate signal as a synchronizing clock, a preceding rate masking circuit masks the preceding rate signal in the second rate signal to output the first rate signal and a D-type flip-flop receives the output of the data row generating portion at the data input terminal thereof and the output of the preceding rate masking circuit at the clock input terminal thereof to generate a data row in synchronism with the first rate signal. As a result, it is possible to provide a synchronous data row generating circuit which operates stably without using the conventional delay elements for adjustment since the data row generating portion therein is composed of synchronous circuits.

Synchronous data row generating circuit

A circuit for automatically adjusting duty cycle of an output clock signal is provided. The circuit comprises a monostable multivibrator for receiving an input clock signal at its clock terminal and outputting an output clock signal, a frequency dividing circuit for dividing down the input clock signal by 1/N, an inverter for inverting an output of the frequency dividing circuit, an integrating circuit for receiving the output clock signal, a comparator for receiving an output of the integrating circuit and a reference voltage corresponding to a desired duty cycle, a D-type flip-flop for receiving an output of the comparator at its data terminal and an output of the inverter at its clock terminal, an AND gate for receiving an inverse output of the D-type flip-flop and the output of the frequency dividing circuit, and a counter for receiving a reset signal at its reset terminal and an output of the AND gate at its clock terminal, and for counting a set data which is input to the monostable multivibrator, wherein the monostable multivibrator outputs the output clock signal having a pulse width corresponding to the set data.

Automatic clock duty cycle adjusting circuit

A timing signal delay circuit comprises a counter placed with first delay setting data (21-24) for counting a first clock signal (12) in response to an input timing pulse (11), and a first flip-flop circuit which has a D-input supplied with the output of the counter (1) and a clock input supplied with a second clock signal of the same timing frequency as the first clock signal. For doubling resolution of the delay which the input timing pulse undergoes, there are provided an exclusive-OR gate (4) supplied with a second dealy data signal (31) and a third clock signal (14) of the same timing as the second clock signal (13), an AND gate (5) supplied with the output of the exclusive-OR gate (4) and that of the first flip-flop (3), and a second flip-flop supplied with the output of the AND gate (5) and a fourth clock signal (15) having twice as high frequency as that of the first clock (12). The input timing pulse can be delayed with high resolution or accuracy.

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Tokyo, Japan

Takafumi Uehara