Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Takafumi Taguchi

Hiromitsu Mashita

Toshiya Kotani

Chikaaki Kodama

Fumiharu Nakajima

Ryota Aburada

Katsumi Iyanagi

Tohru Ozaki

Toshiki Hisada

Takashi Nakazawa

Taiga Uno

Hidefumi Mukai

Takayuki Toba

Ryuji Ogawa

Michiya Takimoto

According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)second sidewall film matching a pattern of a n(where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2)&#xd7;(&#x3bb;/NA) or less when an exposure wavelength of an exposure device is &#x3bb;, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

Semiconductor device having contacts in drawing area and the contacts connected to word lines extending from element formation area

Method of manufacturing semiconductor device using sidewall films for pitch multiplication in forming interconnects

A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.

Method of manufacturing semiconductor device and computer readable medium for storing pattern size setting program

A pattern dimension calculation method according to one embodiment calculates a taper shape of a mask member used as a mask when a circuit pattern is processed in an upper layer of the circuit pattern formed on a substrate. The method calculates an opening angle facing the mask member from a shape prediction position on the circuit pattern on the basis of the taper shape. The method calculates a dimension of the circuit pattern according to the opening angle formed at the shape prediction position.

Pattern dimension calculation method and computer program product

A pattern generating method includes: extracting, from a shape of a pattern generated on a substrate, a contour of the pattern shape; setting evaluation points as verification points for the pattern shape on the contour; calculating curvatures on the contour in the evaluation points; and verifying the pattern shape based on whether the curvatures satisfy a predetermined threshold set in advance.

Pattern generating method, method of manufacturing semiconductor device, computer program product, and pattern-shape-determination-parameter generating method

According to one embodiment, a semiconductor device includes a plurality of first interconnects, a second interconnect, a third interconnect, and a plurality of conductive members. The plurality of first interconnects are arranged periodically to extend in one direction. The second interconnect is disposed outside a group of the plurality of first interconnects to extend in the one direction. The third interconnect is provided between the group and the second interconnect. The plurality of conductive members are disposed on a side opposite to the group as viewed from the second interconnect. A shortest distance between the first interconnect and the third interconnect, a shortest distance between the third interconnect and the second interconnect, and a shortest distance between the first interconnects are equal. A shortest distance between the second interconnect and the conductive member is longer than the shortest distance between the first interconnects.

Semiconductor device and method for manufacturing same

Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.

Pattern generating method, method of manufacturing semiconductor device, and recording medium

A pattern data creating method comprising: referring to a first correspondence relation between an amount of dimension variation between a first pattern formed on a substrate and a second pattern formed by processing the substrate using the first pattern and either one of a pattern total surface area and a pattern boundary length of the first pattern; and creating pattern data for forming the first pattern.

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Kanagawa, Japan

Takafumi Taguchi