Renesas Technology Corp.

Other

Hitachi Ulsi Systems Co., Ltd.

Renesas Electronics Corporation

Hitachi Yonezawa Electronics Co., Ltd

Hitachi, Ltd.

Takafumi Nishita

Kazunari Suzuki

Hiromichi Suzuki

Fujio Ito

Akihiko Kameoka

Kunihiko Nishi

Kunihiro Tsubosaki

Yoshinori Miyaki

Michiaki Sugiyama

Takashi Miwa

Noriyuki Takahashi

Masahiro Ichitani

Masayuki Suzuki

Nobuhiro Kinoshita

Kazunori Hasegawa

Kenichi Imura

Kouji Tsuchiya

Takao Matsuura

Jumpei Konno

Takanori Hashizume

Toshiaki Morita

Bunshi Kuratomi

Tomoo Matsuzawa

Masachika Masuda

Tamaki Wada

Fukumi Shimizu

Tomoko Higashino

Seiichi Tomoi

Kenji Hanada

Naoki Kawanabe

Masaki Nakanishi

Hiroshi Ohno

Kunio Shigemura

Masayoshi Shinoda

Toshiaki Ishii

Takashi Kikuchi

Ryozo Takeuchi

Ryosuke Kimoto

Junpei Kusukawa

Masanori Shibamoto

Hiroshi Koyama

Hiroshi Kawakubo

Yasuyuki Nakajima

Youichi Kawata

Chikako Imura

Masaru Kawakami

Masaru Yamada

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width Wand a narrow part (a second portion) with a second width W. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Semiconductor device

Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.

Method of manufacturing semiconductor device and semiconductor device

Method of manufacturing semiconductor device

A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component, an integrated chip component, and a semiconductor chip ICby Pb-free solder is carried out by heat treatment at a temperature below 280&#xb0; C. using a heat block. Solder connection of a semiconductor chip ICby high-melting point solder is carried out by heat treatment at a temperature of 280&#xb0; C. or higher using a hot jet. Thus, the semiconductor chip ICcan be solder connected to PCBusing high-melting point solder without the following troubles: damage to the PCBdue to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip ICcan be mounted over the PCBwith high connection strength.

Electronic device and manufacturing method of the same

Improvement in the yield of a semiconductor device is aimed at. When extruding a molded body with the ejector pin which performs advance-or-retreat movement at the projecting portion which projects from this bottom face in the bottom face of a mold cavity corresponding to the surface and the mounting side of a molded body after forming a molded body, depressed portions being formed in the surface and the mounting side by projecting portions, they can extrude. When accumulating molded bodies themselves in the baking step after a resin molding step and performing bake, by arranging the resin burr which furthermore withdrew from the surface and the mounting side in the depressed portion, bake can be performed in the condition that the accumulated molded bodies are stuck. Therefore, the form of deformation of a warp etc. of each molded body or a lead frame, can be made uniform, and, as a result, improvement in the yield of QFP (semiconductor device) is aimed at.

Method of manufacturing a semiconductor device

The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.

A semiconductor device with improved the adhesion between bonding pads and ball portions of gold wires is provided to improve the reliability of a semiconductor device. About 1 wt. % of Pd is contained in gold wires for connection between electrode pads formed on a wiring substrate and electrode pads (exposed areas of a top layer wiring formed mainly of Al) formed on a semiconductor chip. In bonded portions between the electrode and ball portions of the gold wires, an interdiffusion of Au and Al is suppressed to prevent the formation of AuAl after PCT (Pressure Cooker Test). Thus, a desired bonding strength is obtained even when the pitch of the electrode pads is smaller than 65 &#x3bc;m and the diameter of the ball portion is smaller than 55 &#x3bc;m or the diameter of the wire portion of each gold wire is not larger than 25 &#x3bc;m.

Semiconductor device having improved adhesion between bonding and ball portions of electrical connectors

For molding semiconductor chips on a wiring substrate matrix with a sealing resin, the wiring substrate matrix is placed on a lower die cavity block of a lower die, and, thereafter, an upper die is brought down, whereby an outer peripheral portion of a cavity of the upper die comes into abutment against an outer peripheral portion of a main surface of the wiring substrate matrix, causing the substrate matrix to be deformed a sufficient extent to prevent resin leakage. Thereafter, block pins provided on the upper die push down the lower die cavity block. Thus, when clamping the wiring substrate matrix using both upper and lower dies, it is possible to suppress or prevent the application of excessive pressure to the wiring substrate matrix and to suppress or prevent deformation or cracking caused by crushing of the wiring substrate matrix. Consequently, the semiconductor device manufacturing yield can be improved.

For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.

A method is provided to improve the adhesion between bonding pads and ball portions of gold wires to improve the reliability of a semiconductor device. About 1 wt. % of Pd is contained in gold wires for connection between electrode pads formed on a wiring substrate and electrode pads (exposed areas of a top layer wiring formed mainly of Al) formed on a semiconductor chip. In bonded portions between the electrode and ball portions of the gold wires, an interdiffusion of Au and Al is suppressed to prevent the formation of AuAl after PCT (Pressure Cooker Test). Thus, a desired bonding strength is obtained even when the pitch of the electrode pads is smaller than 65 &#x3bc;m and the diameter of the ball portion is smaller than 55 &#x3bc;m or the diameter of the wire portion of each gold wire is not larger than 25 &#x3bc;m.

Method of manufacturing a semiconductor device to provide improved adhesion between bonding pads and ball portions of electrical connectors

The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.

Method of manufacturing a semiconductor device and a semiconductor device

Growing community of inventors

Iruma, Japan

Takafumi Nishita