Matsushita Electric Industrial Co., Ltd.

Takafumi Nakashiba

Takahiro Ochi

Mitsuko Takada

In a voltage drop analysis step S, the process calculates a temporal variation of a power source voltage supplied to each cell along a transmission path of a clock signal. In a delay variation rate ratio calculation step S, the process calculates a delay time variation of each cell according to the power source voltage variation. In a clock delay variation amount calculation step S, the process obtains the magnitude of jitter of the clock signal based on the delay time variation.

Clock jitter calculation device, clock jitter calculation method, and clock jitter calculation program

In hierarchical design of a logic circuit by utilizing lower-level blocks of the logic circuit, data on the logic circuit with the hierarchical structure, library data holding primitive information on the logic circuit and timing constraints on the lower-level blocks are input at a data input step. Based on these input data, it is determined whether or not interface specifications of timing constraints on the lower-level blocks match each other at a matching determination step before a constraint converting step of converting the timing constraints on the lower-level blocks into a timing constraint on a higher-level block. Accordingly, it is possible to avoid generation of an excessively reduced or rigorous timing constraint on the higher-level block resulting from mismatching between interface specifications of timing constraints on the lower-level blocks.

Growing community of inventors

Kyoto, Japan

Takafumi Nakashiba