Kabushiki Kaisha Toshiba

Takafumi Ikeda

Hideo Kato

Tokumasa Hara

Yasuhiko Honda

Masao Kuriyama

Hidetoshi Saito

Tatsuya Hiramatsu

Naoto Tomita

Hiroyuki Ishii

Noboru Shibata

Kazuhiro Shimizu

Toshifumi Minami

Shoko Kikuchi

Yuuichi Tatsumi

Yoshio Mochizuki

Takahito Nakazawa

Hideaki Maekawa

According to one embodiment, a semiconductor device includes a stacked structure that is formed by laminating a first insulating film, first conductive layer, second insulating film and second conductive layer on a semiconductor substrate and in which the first and second conductive layers are connected with a via electrically, an interlayer insulating film formed to electrically separate the second conductive layer into a first region including a connecting portion with the first conductive layer and a second region that does not include the connecting portion, a first contact plug formed on the first region and a second contact plug formed on the second region. An isolation insulating film is buried in portions of the substrate, first insulating film and first conductive layer in one peripheral portion on the second region side of the stacked structure and the second contact plug is formed above the isolation insulating film.

Semiconductor device

A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region. The protective pattern comprises a first element separation region formed on the semiconductor substrate, a second element separation region formed on the semiconductor substrate and having a width smaller than that of the first element separation region, a first element region formed between the first element separation region and the second element separation region, a first gate layer formed on the first element separation region, a wiring layer formed on the first gate layer, a passivation layer formed above the wiring layer, a second element region, an insulation film formed on the second element region, and a second gate layer formed on the insulation film, the first element separation region, the first element region, the second element separation region and the second element region being located in this order from the nearer side of the circuit element region.

Semiconductor device having a protection pattern with two element separation regions

According to an aspect of the present invention, there is provided a method for fabricating a nonvolatile semiconductor memory device including a memory cell being formed in a first region of a semiconductor substrate and a periphery circuit being formed in a second region of the semiconductor substrate, including forming a first gate electrode material film over the semiconductor substrate via a first gate insulator in the first region, etching the first gate electrode material film and the first gate insulator using a mask having a first opening in a first element isolation of the first region, etching the semiconductor substrate to a first depth to form a first isolation groove, forming a first insulation isolation layer in the first isolation groove, forming a second insulator on the first insulation isolation layer and on the first gate electrode, removing the second insulator by anisotropic etching, etching an upper portion of the first gate electrode to a second depth to form a first concave portion on the upper portion of the first gate electrode, etching the first side-wall film and the first insulation isolation layer to a depth at a bottom surface of the first concave portion, forming a second gate insulator on the upper portion of the first gate electrode, and forming a second gate electrode material film on the second gate insulator.

Nonvolatile semiconductor memory device and method for fabricating nonvolatile semiconductor memory device

A semiconductor device includes a memory cell array including a plurality of cores, each of said cores including one block or a plurality of blocks. The semiconductor device further includes a first power supply line which is provided commonly for said plurality of cores and which provides a data reading power supply potential; a second power supply line which is provided commonly for said plurality of cores and which provides a data writing or erasing power supply potential; and a power supply line switching circuit which is provided for each of said plurality of cores and which selectively connects a corresponding one of said plurality of cores to said first power supply line or said second power supply line in accordance with whether said corresponding one of said plurality of cores is in a data read mode or a data write or erase mode.

Semiconductor device that enables simultaneous read and write/read operation

A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.

A memory cell array has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided for writing data in memory cells in cores selected on the basis of a write command and for erasing data from selected blocks in cores selected on the basis of an erase command. Thus, there is realized a free core system capable of reading data out from memory cells in unselected cores while writing/erasing data in cores selected by the core selecting part.

Semiconductor device that enables simultaneous read and write/erase operation

A pulse generator circuit provides a capacitor, a constant current source circuit for charging the capacitor at a constant current in response to an input signal, and a differential amplifier circuit for comparing a charge voltage in the capacitor with a predetermined reference voltage Vref, thereby outputting a pulse signal.

Pulse generator circuit and semiconductor memory provided with the same

A redundancy memory cell array is arranged at an end of a main memory cell array in the column direction. Common bit lines and common column lines are arranged on the main memory cell array and the redundancy memory cell array. A disconnection circuit is arranged between the main memory cell array and the redundancy memory cell array for connecting or disconnecting bit lines or column lines. A column selection switch is arranged at an end of the redundancy memory cell array. A redundancy circuit disconnects bit lines or column lines by means of a disconnection circuit when an address signal specifies a defective address.

Growing community of inventors

Yokohama, Japan

Takafumi Ikeda