Canon Kabushiki Kaisha

Takafumi Fujiwara

Atsushi Date

Noboru Yokoyama

Tadaaki Maeda

Katsunori Kato

Keigo Ogura

Kohei Murayama

An image input/output control apparatus includes a control device for controlling input/output of image data with an external apparatus, plural image processing devices for performing predetermined image processes to the image data, and plural data transfer devices for connecting each of the plural image processing devices and the control device like a ring and performing data transfer among them. The plural image processing devices and the control device are composed respectively on different units, whereby the structure of the apparatus can be easily changed, and a decrease in processing speed due to the competition for buses can be reduced without increasing the number of parts necessary for bus control.

Image input/output control apparatus, image processing apparatus, image processing method, data communication apparatus, and data communication method

An image processing apparatus includes a production unit that can produce data by putting original image data into a first region and copy-forgery-inhibited-pattern image data into a second region, and a processing unit that can perform predetermined processing to the original image data put in the first region. The image processing apparatus further includes a composite image data producing unit that can produce composite image data based on both of the original image data to which the predetermined processing is performed and the copy-forgery-inhibited-pattern image data put in the second region of the data.

Image processing apparatus, control method for the image processing apparatus, and storage medium storing computer program for executing the control method of the image processing apparatus

A memory system includes a memory and a plurality of memory controllers for accessing the memory. One of the plurality of memory controllers synchronizes the one of the plurality of memory controllers with the plurality of memory controllers.

Memory controller configuration system and method

In a bus, which is provided with a switch having a plurality of master ports and a plurality of slave ports and can connect each of the plurality of master ports to an arbitrary port of the plurality of slave ports, an address phase that issues an address and a command and a data phase that issues write data are separated, and an address phase of next transaction can be issued before the data phase is completed. This improves performance of a system, in which a plurality of master modules and slave modules are connected through the bus.

Control method for bus provided with internal switch

In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

Method of arbitration for bus use request and system therefor

A P bus from a CPU, an MC bus from a system memory, an IO bus to which an input/output device has been connected, and a G bus for transferring image data of a scanner/printer controller are connected to a system bus bridge (SBB). The SBB connects any of the P bus, G bus and IO bus as a master and any of the MC bus and IO bus as a slave in dependence upon a request from a master. At this time the P bus and IO bus can be connected in parallel with the G bus and MC bus. As a result, access to the memory by the scanner/printer controller can be carried out in parallel with use of the input/output device by the CPU. This makes it possible to process a large quantity of data, such as image data, efficiently.

Bus management based on bus status

The present invention efficiently compresses image data, and stores and manages the compressed data. Image data is compressed in tile unit having predetermined pixels and data packing is performed. The compressed data is compared with compressed data of a preceding packet. If these compressed data are different, the packet data is stored in a memory, and an entry address of the compressed data is stored in a packet table. Meanwhile, if the compressed data is equal to the compressed data of the preceding packet, the compressed data is not stored, but an entry address of the compressed data of the preceding packet is stored in a record of interest in the packet table, and a flag indicative of repetition of the preceding address is set in the packet of interest.

Image processing apparatus and method, and storage medium

Method of delaying bus request signals to arbitrate for bus use and system therefor

Bus control apparatus solves the problem that a high-speed bus which supports only burst transfer cannot be used when the boundary of a transfer memory address is not coincident with a unit boundary. A scanner controller and printer controller connected to a G bus capable of performing only burst transfer and a B bus capable of performing even single transfer determine from the address and data length of data to be transferred whether the data does not match the memory boundary. If the data does not match this boundary, a data portion which is not accommodated within the burst transfer unit is single-transferred using the B bus. A data portion which is accommodated within the burst transfer unit is burst-transferred using the G bus.

Bus control apparatus

A scanner is connected to a G bus and a B bus by way of a scanner controller and a G bus/B bus interface (GBI). A printer is connected in a similar manner. Furthermore, the scanner controller is connected directly to a printer controller with a CP bus. The GBI is capable of performing DMA transfer and data can be transferred between the GBIs. Furthermore, data can be transferred by way of the G bus and a RAM or the B bus and the RAM. The GBI is connected to the scanner controller and the printer controller by way of FIFOs, respectively. Accordingly, an image input/output control system according to the present invention is capable of absorbing differences in data transfer speeds and can be connected to various kinds of scanners and printers.

Image input/output control system

The control apparatus reads the value of an external switch, and checks whether the apparatus serves as a control side or subordinate side. If the control apparatus serves as a subordinate side, it waits until the control side writes a configuration through a bus. If the control apparatus serves as a control side, it sets necessary values in itself, and writes a configuration in a device on the bus. In this way, the control apparatus can operate as both the control side and subordinate side.

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Tokyo, Japan

Takafumi Fujiwara