Sony Corporation

Sony Olympus Medical Solutions Inc.

Takaaki Yamada

Toru Karashima

Takaaki Morimura

Naofumi Yanagihara

Hiroshi Okada

Kazutoshi Shimizume

Yukio Tsuda

Yoshimi Hirata

Shuichi Sato

Masayoshi Abe

Yoshio Osakabe

Tatsuya Sugioka

Hisayoshi Yamoto

Hiroki Kihara

Chihiro Arai

Takeo Sekino

Teruaki Aoki

Akira Yamakoshi

Hiroshi Yamagata

Kazuhiro Takeda

Hisashi Owa

Yukio Shimomura

Kazuo Kumano

Takahide Kadoyama

Atsushi Kamo

Yasushi Nakamoto

Masanori Okayama

Taichi Niki

Makoto Hirabayashi

There is provided a medical display control apparatus including: a display control section configured to control a display of a medical captured image for a right eye and a medical captured image for a left eye captured by an imaging device that images an observation target on a display screen and a display of a pointer object on the display screen. The display control section causes the pointer object to be displayed in correspondence with a depth position of the medical captured image for the right eye and the medical captured image for the left eye.

Medical display control apparatus and display control method

A communication system includes: a transmitter adapted to transmit a synchronizing clock and serial data synchronous with the synchronizing clock over a line at low amplitude; and a receiver adapted to receive the serial data and synchronizing clock from the transmitter. The receiver includes an amplifier adapted to amplify the received synchronizing clock of low amplitude to restore the clock to its original amplitude, a latched comparator adapted to latch the received serial data in synchronism with a reproduction clock, and a phase-locked circuit.

Communication system, receiver and reception method

A power switch and connector that are conventionally included in a body are formed in spaces created at the outer ends of the shafts of hinges other than the body and a display, whereby the body is thinned. Electronic device comprises a body, a display, and a hinge that joins the body and display so that they can be freely opened or closed. A power switch is formed at an end of the shaft of the hinge. Furthermore, the electronic device comprises the body, the display, and another hinge that joins the body and display so that they can be freely opened or closed. A port of a connector opens at an end of the shaft of the hinge.

Electronic device

A semiconductor element capable of reducing noises of a circuit propagating to another circuit through a seal ring is provided. A semiconductor element includes, on a surface of a semiconductor substrate: a plurality of circuits; a ring-shaped seal ring surrounding the plurality of circuits; and wiring connecting between the seal ring and an external low-impedance node.

Semiconductor element, semiconductor device and mounting board

The present invention provides a semiconductor device, including: a first semiconductor chip, and a second semiconductor chip connected to the first semiconductor chip through a plurality of bumps having not only a number of main bumps necessary for operation between the chips but also a predetermined number of measurement and control input bumps. Each of the first and second chips includes a plurality of measurement path switches individually connected to the main bumps, a plurality of current path switches connected to connecting points between the main bumps and the measurement path switches, and a control circuit for the measurement path switches, the first semiconductor chip further including a plurality of measurement and control terminals for inputting a control signal of the control circuit and supplying fixed current to be supplied to the current path switches and then measuring the voltage at the connecting points.

Semiconductor device, semiconductor integrated circuit and bump resistance measurement method

An analog signal, for example, a video signal is divided into a high frequency signal and a low frequency signal by a high-pass filter and a low-pass filter. A high speed analog-to-digital converter (ADC) converts the high frequency signal to a first digital code while a low speed but high precision ADC converts the low frequency signal to a second digital code. A synthesizer combines the first and second digital codes and outputs a digital code as the result of the conversion. Therefore, analog-to-digital conversion with a high speed, high precision, and high resolution can be realized.

Digital to analog converter

A signal-processing circuit adapted for signal compression and expansion performed in the transmitter and receiver of mobile communication equipment. The signal-processing circuit comprises a multiplication type D/A converter to which an analog signal is applied, a level detector circuit that detects the level of the analog signal, and an A/D converter. The D/A converter converts the analog input signal into an analog output signal having an amplitude corresponding to digital control data. The A/D converter digitizes the output signal from the level detector circuit and supplies it as said digital control data to the D/A converter. These circuits can be fabricated from CMOS circuits.

Signal compression or expansion circuit for mobile communication

A communication circuit system of an IC card etc. including a voltage drop circuit having a complementary type transistor circuit comprising a p-channel and an n-channel transistor connected together, the circuit being connected to a power source voltage and generating a voltage corresponding to the sum of the threshold voltages of the p-channel transistor and n-channel transistor and supplying the same to a load circuit; an oscillation circuit having a complementary MOS inverter, a capacitor connected to the input side of the complementary MOS inverter, and resistance elements connected between the input and output of the complementary MOS inverter; and a wave detection circuit having a first and second MOS transistors with drains and gates connected to each other and a current source, nodes between the drains and the gates of the first and second MOS transistors being connected to the current source, the gate of the first MOS transistor being connected to a signal input line, and the current capacity of the second MOS transistor being set larger than the current capacity of the first MOS transistor.

Communication circuit with voltage drop circuit and low voltage drive

A quantizing number is determined using multiple stages of code amount estimating circuits. Thus, an optimum quantizing number may be selected from among a number of quantizing numbers which is not limited to the number of code amount estimating circuits. The optimum quantizing number is used to quantize a set of blocks of orthogonally transformed image data. The quantized data are encoded using a variable length code. The optimum quantizing number is the one which results in the greatest amount of data that is within a predetermined threshold, permitting an amount of encoded data to be recorded on a magnetic tape in a fixed format.

Method and apparatus for encoding an image signal using a multi-stage

Apparatus for compression encoding video signals, comprising block segmenting circuits for segmenting a vertical interval, such as a field or frame, of video picture elements into a plurality of blocks of picture elements. An orthogonal transformation, such as discrete cosine transformation, of respective blocks is obtained, resulting in a two-dimensional array of transform coefficients of different values, the array being partitioned into respective areas. Each area is quantized with a respective quantizing value that differs for different areas. Preferably, a transform coefficient is quantized by dividing the value of the transform coefficients in an area by a divisor 2.sup.n/2, where n is an integer that differs in different areas. The areas of the two-dimensional array of transform coefficients are formed by partitioning the array in a direction substantially perpendicular to the oblique frequency axis of that array.

Apparatus for compression encoding video signals

A digital VCO is disclosed which comprises a ring oscillator formed of a plurality of inverters connected in series, each inverter being capable of controlling its delay amount, a frequency controlling circuit for controlling the oscillation frequency of the ring oscillator to coincide with a reference frequency, a selector switch for selecting specified output taps from output taps, each thereof being provided for each of the plurality of inverters, to take out the outputs therefrom, and switching control means for controlling the output taps from which the outputs are taken out to be cyclically switched through the selector switch.

Digital voltage controlled oscillator having a ring oscillator with

In a digital-to-analog converter for converting a received digital signal having N bits and a sampling frequency fs to an analog signal; digital interpolation filter receives the digital signal and generates a modified digital signal having a number of bits less than N and a sampling frequency greater than fs, pulse width modulator receives the modified digital signal and generates a pulse signal having pulse widths which correspond to the modified digital signal, output buffer having a complementary metal oxide semiconductor (CMOS) inverter circuit including P channel and N channel transistors having respective resistance values receives the pulse signal and low-pass filter receives the output signal from the output buffer, wherein the digital interpolation filter, the pulse width modulator and the output buffer are formed in an integrated circuit, and when the transistors are conductive the resistance values of the P channel and N channel transistors are set equal to each other by adjusting a voltage applied to the integrated circuit substrate so as to improve the signal-to-noise ratio of the produced analog signal.

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Kanagawa, Japan

Takaaki Yamada