Fujitsu Corporation

Nippon Telegraph and Telephone Corporation

Takaaki Wakisaka

Tomohiro Ishihara

Haruo Yamashita

Atsuki Taniguchi

Toshiyuki Sudo

Ryuichi Kondo

Jun Tanaka

Masato Okuda

Kazuto Nishimura

Nobuhiro Fujimoto

A re-calculator circuit obtains the MCR value of each connection stored in an MCR storage unit, and performs a calculation in such a way as to impartially distribute the available rate band of a FIFO among active connections. The re-calculator circuit stores a rate band attached to the MCR value of each active connection by this calculation, in a virtual MCR storing unit as a virtual MCR value. This rate measurement unit refers to the virtual MCR value stored in the virtual MCR storage unit, and judges whether or not the input cell rate of each active connection exceeds the virtual MCR value. This result is inputted to an input control unit. The input control unit examines the input cell rate information and congestion monitoring information inputted from a queue length monitor unit for monitoring the volume of cells buffered in the FIFO, and determines whether to discard the incoming cell or to input the cell to the FIFO.

Apparatus and method for managing rate band

The present invention relates to a buffer control apparatus and method. In a buffer control apparatus for controlling storage process for a common buffer which is commonly used for a plurality of routes and temporarily stores data received from the routes, the buffer control apparatus comprises a route discriminating section for identifying the routes of the received data; a storage section for storing at least information concerning a storing position for the received data within the common buffer for each of the routes; and a control section for performing a control operation for virtually storing, route by route, the received data into the common buffer according to a result of route identification in the route discriminating section and the information concerning the storing position in the storage section, whereby the storage control in the common buffer is performed such that the common buffer can be virtually used as discrete buffers, in order to secure minimum band for each of the routes without increasing the capacity of the buffer and complicating the readout control for the buffer.

Buffer control apparatus and method

According to the present invention, when a current system is switched to a spare system in a transmission system in an asynchronous transfer mode, empty cells transmitted in the current and spare systems are detected, and thereby a timing for switching the current system to the spare system is determined. When no phase difference is existent between the current and spare systems, an empty cell is detected in both the current and spare systems at the same time. Therefore, the current system is switched to the spare system, when an empty cell is detected in both the current and spare systems at the same time. When a shade difference is existent, if an empty cell is detected either in the current or spare systems, another empty cell is inserted in to the systems. Then, the data of the empty cell in a spare system is saved. After the empty cell in a current system passes, the current system is switched to the spare system. When a phase difference of at least one cell is existent, and if an empty cell comes earlier in current system, empty cell are kept inserted form when the empty cell is detected in the current system until an empty cell is detected in the spare system. After that, the current system is switched to the spare system. When an empty cell comes earlier in a spare system, the data of the cell in the spare system is saved from when the empty cell is detected until an empty cell is detected in the current system. After that, the current system is switched to the spare system.

Apparatus and method for non-stop switching in asynchronous transfer mode

A synchronous circuit includes a first circuit block operating in synchronism with a first clock signal, and a second circuit block operating in synchronism with a second clock signal having a frequency lower than that of the first clock signal. The first circuit block includes a frame synchronizing circuit for detecting a synchronous pattern contained in input data having a frame format having a supervisory control data part and an information part, the supervisory control data part including pointer information indicative of a beginning of the information part. The first circuit block includes a synchronizing unit for generating, from the synchronous pattern, a synchronizing control signal for synchronizing the operation of the second circuit block with the operation of the first circuit block. The first circuit block includes a pulse generator for generating a first frame pulse signal from the first clock signal. The second circuit block includes an information part detecting unit for generating a second frame pulse signal having a frequency lower than that of the first frame pulse signal from the second clock signal and the synchronizing control signal, the first frame pulse signal being synchronized with the beginning of the information part.

Synchronization circuit for establishing frame synchronism using

A phase matching circuit for realizing accurate data transmission and reception through phase shift control only during a data invalid region. The phase matching circuit includes an input buffer for taking first data with a first clock; an output buffer sending second data with a second clock; a phase detector for comparing the phases of first and second clocks and detecting a phase difference within a predetermined value; a phase control unit for directly outputting the first data to the output buffer when the phase difference within the predetermined value is not detected or for outputting the first data phase shifted to the output buffer, and for converting the first data synchronized with the first clock to the second data of the same content as the first data synchronized with the second clock in the same frequency as the first clock; an invalid data region detector for detecting an invalid region of first data; and a phase shifter controller for inhibiting phase shift control in the phase control unit when the invalid data region detector does not detect the invalid region and for allowing phase shift control in the phase control unit when the invalid data region detector detects the invalid region.

Phase matching circuit

A phase adjusting circuit for adjusting a phase of each bit of serial data by synchronizing with a system clock. The phase adjusting circuit includes a plurality of registers. Each bit of data is input into a corresponding one of the plurality of registers in a predetermined cyclic order, synchronized with a receiving clock which is extracted from the data, and outputting outputs of the registers in parallel. The outputs are each selected in a selector circuit under a control of the selector control signal in the same order as the above input to the registers. The selector control signal is generated by detecting a phase relationship between phases of the receiving clock and the system clock, and generating a selector control signal having a phase which is determined according to the phase relationship. Then, each bit of the above selected output is synchronized with the system clock.

Phase adjusting circuit

A reception processing unit receives digital data in successive data frames, each frame comprising a supervisory data field and an associated information data field and, further, a negative stuff or a positive stuff in accordance with need, and detects the head position of the information data field. An enable signal is produced only during and throughout a time interval in which the information data field appears in each successive, received data frame; a count operation of a counter is performed only during the interval of the enable signal. The head position is detected each time the counter finishes counting a number of bytes equal to the fixed length of the information data field.

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Kawasaki, Japan

Takaaki Wakisaka