Hitachi, Ltd.

Takaaki Toyama

Yasuo Murakami

Yusho Futami

Masahide Minowa

Yoshihiro Ashi

Nobuyuki Yamamoto

Takashi Seki

Akihiko Takase

Takahiko Kozaki

Masahiro Takatori

Norihiko Moriwaki

Toshiyuki Saito

Masaru Murakami

Munetoshi Tsuge

Mitsuhiro Wada

Yozo Oguri

Kaori Nakayama

Masao Nakayama

Yu Mitsui

Kouichi Asao

Kenichirou Tomizawa

Taichi Hiramatsu

Shuuichi Maruyama

Yoshihiro Sakae

Tetsuo Kano

Hitoshi Yajima

A MVAC spoofed frame or a loop frame generated by a user is prevented from obstructing communication and the source port ID of a fraud is reported to the network administrator. A MAC frame forwarding apparatus adds the input port ID and the source MAC address of a received frame. The MAC frame forwarding apparatus has a frame forwarding management table and a frame discarding management table. The frame discarding management table has a MAC address to be discarded, indicating a received frame to be discarded if the address matches the source MAC address of the received frame, a target port ID, and the number of discarded frames. A management apparatus discards a received frame if the source MAC address matches the MAC address to be discarded and counts the number of discarded frames. If the number of discarded frames exceeds a predetermined level, the port ID, the MAC address, and the number of discarded frames are reported to the management apparatus, and the source port of the fraud is reported to the administrator.

Frame forwarding apparatus

An ATM network for synchronously perform a path connection control at a plurality of nodes, wherein path control data are preliminarily supplied to the nodes from a network management system before a designated operation time. Each node generates a current time synchronously with a network synchronous clock, selects path control data by comparing the designated operation time of the control data with the current time, and autonomously executes a path connection control in accordance with the selected path control data.

Communication network system and method for synchronously controlling path connection

Provided is a cell exchanging device which realizes switching of an AAL2 connection level using an existing ATM switch, thus preventing deterioration of a transfer quality of other ATM cells. In an input-side ATM line corresponding section, provided are an ATM cell demultiplexing section 113-I-1 for extracting and separating only an AAL2 cell from an ATM cell, an AAL2 DMX 113-I-2 for converting from the AAL2 cell to an AAL2 partial fill cell, and an ATM cell multiplexing section 113-I-4 for multiplexing and packing the ALL2 partial fill cell and the ATM cell other than AAL2. Before entering to the ATM switch, a priority order of each ATM cell is determined based on class information presented in the ATM line corresponding section, and reading-out from the ATM cell multiplexing section is controlled. Similarly, also in an output-side ATM line corresponding section, at the time of a transfer to a transmission path, a priority order of each ATM cell is determined based on class information presented in the input-side ATM line corresponding section and a reading-out is performed.

Cell exchanging device

In a variable length switch for exchanging CPS-packets by AAL , an effective variable length packet switch without limiting capacitance of a switching section is provided when the CPS-packets are loaded on an ATM cell and exchanged. An interface section receives the ATM cell in which the CPS-packets are multiplexed and packed, disassembles the received ATM cell and demultiplexes and unpacks the CPS-packets loaded on the ATM cell. When output paths of the plurality of the CPS-packets are identical, the CPS-packets are transferred by multiplexing and packing them in the same connection. In an interface - to -N on a transmission side, a cell transferred from the switching section is disassembled, and the CPS-packet are multiplexed and packed in a cell corresponding to an output path of the CPS-packets.

Variable length packet switch

A method and a system for multiplexing voice packets without delay variation even if the number of multiplexed channels is increased, wherein a packet buffering unit receives compressed voice data, and stores voice data groups during voice activity intervals in each channel as talk; a scheduling FIFO block sequentially stores the channel numbers of a predetermined number of multiplexed channels which are read according to priority over the other channels, thereby controlling reading contention. A write decision block controls writing of talk spurts in the buffer areas of the respective channels in a packet buffering unit and also controls writing of the channel numbers in the scheduling FIFO block. A scheduling FIFO controller selects channel numbers from the scheduling FIFO block and a read decision block outputs voice packets by controlling the multiplexing sequence of talk spurts of the selected channel numbers.

Method and system for multiplexing packets

An ATM switch that can be expanded to form a large scale ATM switch with minimal hardware additions. The ATM switch includes a plurality of ATM switch units arranged in parallel, a plurality of cell distributors arranged on the input side of the ATM switch units, and a plurality of cell assemblers arranged on the output side of the ATM switch units. Each of the cell distributors distributes ATM cells received from a plurality of incoming highways to a buffer memory having a plurality of queues corresponding to the output ports of the ATM switch units, namely destinations of the ATM cells, and stores the ATM cells to the queues in the buffer memory. Each cell distributor reads ATM cells having the same destination information, and outputs such ATM cells to respective ones of the ATM switch units in parallel. Each of the ATM switch units independently exchanges the received ATM cell in parallel with the other ATM switch units. Each of the cell assemblers multiplexes ATM cells received from the ATM switch units in a manner to preserve the time sequential order of the ATM cells, and outputs the ATM cells to one of a plurality of outgoing highways. A desired increase in the capacity of the ATM switch is implemented by adding an ATM switch unit between the cell distributors and the cell assemblers, thereby allowing for an increase in hardware in proportion to the desired increase in capacity.

ATM switch

For reducing the scale of a multiplexer, a lower speed ATM interface block, an interface block for SDT mode circuit emulation, and an interface block for UDT mode circuit emulation perform processing for terminating services provided by lower speed transmission lines accommodated therein, and part of AAL processing, which is pre-processing depending on a service, for generating ATM cells from signals received by a terminated service, and send the processed signal to a higher speed line interface using a previously assigned time slot on a time-division bus. The higher speed line interface once stores the signals received from the time-division bus in a buffer, and subsequently performs certain processing including a common portion for respective signals for generating therefrom ATM cells in which the signals are stored in payloads. The generated ATM cells are multiplexed and transmitted onto a higher speed transmission line.

Multiplexing apparatus for transit of signals between service provided

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Fujisawa, Japan

Takaaki Toyama