Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Vlsi Limited

Kyushu Fujitsu Electronics Limited

Takaaki Suzuki

Yasuharu Sato

Masao Taguchi

Yasurou Matsuzaki

Shinya Fujioka

Kotoku Sato

Tadao Aikawa

Yoshihiro Takemae

Masafumi Yamazaki

Hitoshi Ikeda

Hirohiko Mochizuki

Atsushi Hatakeyama

Toshiya Uchida

Hideaki Kawai

Junji Ogawa

Kenichi Kawasaki

Yukinori Kodama

Makoto Yanagisawa

Shinnosuke Kamata

Ayako Sato

Akihiro Funyu

Kimiaki Satoh

Hiroyuki Kobayashi

Masao Nakano

Masato Matsumiya

Waichirou Fujieda

Takayuki Nagasawa

Hiroyoshi Tomita

Satoshi Eto

Toshikazu Nakamura

Toshiya Miyo

Takayuki Yoneda

Sumie Kodama, Legal Representative

Noriko Kawamura

Akira Takashima

Hiroshi Gotou

Yoshimasa Yagishita

Nobutaka Taniguchi

Takeo Tatematsu

Tetsuya Hiraoka

Makoto Niimi

Kaname Ozawa

Kazuyuki Aiba

Toyonobu Yamada

Toyomitsu Matsumoto

Tetsuya Endo

Masato Kaida

A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

Multi-port memory based on DRAM core

In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Semiconductor apparatus having a large-size bus connection

A semiconductor integrated circuit is disclosed that operates in synch with a clock signal supplied from an external source, and by a voltage supplied by a power supply. The circuit includes a detection means for detecting that at least one of a frequency of the clock signal and the supply voltage is reduced, and an internal voltage reduction means for lowering an internal voltage of the semiconductor integrated circuit when the detection means detects that at least one of the frequency and the supply voltage is lowered.

Semiconductor integrated circuit device, an electronic apparatus including the device, and a power consumption reduction method

Apparatus to reduce the internal frequency of an integrated circuit by detecting a drop in the voltage and frequency

An external terminal receives an external signal so as to access the first and second memory chips. The test starting terminal receives a test starting signal activated when the first or second memory chip is tested and inactivated when the first and second memory chips are normally operated. The access signal generator converts the external signal to a memory access signal of the first memory chip. The first selector selects the external signal, which is a test signal, during activation of the test starting signal, selects the memory access signal during the inactivation of the test starting signal. That is, during the test modes, the first memory chip can be directly accessed from the exterior. For this reason, the test program for testing the first memory chip alone can be diverted as the test program following an assembly of the semiconductor device.

Semiconductor device

A semiconductor chip is secured in a state deformed into a substantially cylinder shape by a coating material formed on its surface. The deformed semiconductor chip is flip-chip connected to an interposer and sealed with sealing resin onto the interposer. Solder balls are provided, as external terminals, on the other side of the interposer.

Deformable semiconductor device

A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern in the first test mode, generated within the logic chip, or the external test pattern in the second test mode, supplied from the exterior.

A semiconductor memory device has a burst write mode in which predetermined plural command signals are input through a plurality of command pads and a mask control operation in the burst write mode is performed in response to the command signals. Therefore, the mask control in burst write mode is increased in speed to give an improved data transfer rate.

Semiconductor memory device with fast masking process in burst write mode

In a semiconductor integrated circuit device operating in synchronism with a clock supplied from the outside of the device, there is provided a circuit generating, from the clock, an output strobe signal for outputting data from the device and outputting the output strobe signal to the outside of the device.

Semiconductor integrated circuit device

An input circuit has an input buffer and a detection circuit. The input buffer receives an external signal and outputs an internal signal. The detection circuit detects whether or not the external signal is provided. The input buffer outputs the internal signal when an output of the detection circuit indicates that the external signal is provided. This arrangement shortens the lock-on time of an internal circuit (synchronous circuit).

Input circuit and semiconductor integrated circuit having the input circuit

A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.

Semiconductor memory device having an SRAM and a DRAM on a single chip

Growing community of inventors

Kawasaki, Japan

Takaaki Suzuki