Sandisk Technologies Inc.

Takaaki Iwai

Yoshitaka Otsu

Hisakazu Otoi

Shuji Minagawa

James K Kai

Sayako Nagamine

Hirofumi Tokita

Junpei Kanazawa

Yanli Zhang

Ching-Huang Lu

Fumiaki Toyama

Wei Zhao

Tatsuya Hinoue

Masanori Tsutsumi

Akio Nishida

Yuki Mizutani

Tomohiro Kubo

Shunsuke Takuma

Takayuki Maekura

Koichiro Nagata

Hironori Matsuoka

Raiden Matsuno

Makoto Koto

Shigeyuki Sugihara

Takashi Orimoto

Takashi Inomata

Kento Iseri

A three-dimensional memory device includes a source-level structure located over a substrate, an alternating stack of insulating layers and electrically conductive layers located over the source-level structure, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings. The source-level structure includes a lower source-level semiconductor layer including elongated grooves in an upper portion thereof, doped semiconductor source rails located within the elongated grooves, and an upper source-level semiconductor layer. The doped semiconductor source rails are laterally spaced apart from each other along a first horizontal direction and laterally extend along a second horizontal direction. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel that contacts a respective one of the doped semiconductor source rails.

Three-dimensional memory device containing source rails and method of making the same

A semiconductor structure includes an alternating stack of insulating layers and composite layers. Each of the composite layers includes a plurality of electrically conductive word line strips laterally extending along a first horizontal direction and a plurality of dielectric isolation strips laterally extending along the first horizontal direction and interlaced with the plurality of electrically conductive word line strips. Rows of memory openings are arranged along the first horizontal direction. Each row of memory openings vertically extends through each insulating layer within the alternating stack and one electrically conductive strip for each of the composite layers. Rows of memory opening fill structures are located within the rows of memory openings. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.

Three-dimensional memory device containing self-aligned isolation strips and methods for forming the same

A memory die includes source-select-level electrically conductive strips laterally spaced apart by source-select-level dielectric isolation structures, an alternating stack of word-line-level electrically conductive layers and insulating layers; and source strips located on an opposite side of the source-select-level electrically conductive strips. Each of the source strips has an areal overlap with only a respective one of the source-select-level electrically conductive strips. Memory stack structures vertically extend through the alternating stack and a respective subset of the source-select-level electrically conductive strips. A logic die may be bonded to the memory die on an opposite side of the source strips. Each source strip is electrically connected to a respective group of memory stack structures laterally surrounded by a respective source-select-level electrically conductive strip.

Three-dimensional memory device with isolated source strips and method of making the same

A three-dimensional memory device can include at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor material layer, memory stack structures vertically extending through the at least one alternating stack, and a vertical stack of dielectric plates interlaced with laterally extending portions of the insulating layers of the at least one alternating stack. A conductive via structure can vertically extend through each dielectric plate and the insulating layers, and can contact an underlying metal interconnect structure. Additionally or alternatively, support pillar structures can vertically extend through the vertical stack of dielectric plates and into an opening through the semiconductor material layer, and can contact lower-level dielectric material layers embedding the underlying metal interconnect structure to enhance structural support to the three-dimensional memory device during manufacture.

Three-dimensional memory device including through-memory-level via structures and methods of making the same

A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate, a first memory array region and a second memory array region that are laterally spaced apart along the first horizontal direction by an inter-array region therebetween, and memory stack structures extending through the alternating stacks in the first or second memory array region. Each of the alternating stacks includes a respective terrace region in which layers of a respective alternating stack have variable lateral extents within an area of the inter-array region, and a respective array interconnection region laterally offset from the respective terrace region and which continuously extends from the first memory array region to the second memory array region. Each of the alternating stacks has a width modulation along a second horizontal direction that is perpendicular to the first horizontal direction within the area of the inter-array region.

Three-dimensional memory device containing width-modulated connection strips and methods of forming the same

A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a semiconductor material layer, and memory stack structures extending through one of the alternating stacks. Laterally-undulating backside trenches are present between alternating stacks, and include a laterally alternating sequence of straight trench segments and bulging trench segments. Cavity-containing dielectric fill structures and contact via structures are present in the laterally-undulating backside trenches. The contact via structures are located within the bulging trench segments. The contact via structures are self-aligned to sidewalls of the alternating stacks. Additional contact via structures may vertically extend through a dielectric alternating stack of a subset of the insulating layers and dielectric spacer layers laterally adjoining one of the alternating stacks.

Three-dimensional memory device containing eye-shaped contact via structures located in laterally-undulating trenches and method of making the same

A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate. Each of the alternating stacks laterally extend along a first horizontal direction, and neighboring pairs of the alternating stacks are laterally spaced apart along a horizontal direction by laterally alternating sequences of memory openings and dielectric pillar structures. Each of the memory openings contains a respective memory opening fill structure that includes a dielectric core, a first vertical semiconductor channel, a second vertical semiconductor channel, a first memory film, and a second memory film. The dielectric core contacts a pair of dielectric pillar structures among the dielectric pillar structures of the laterally alternating sequences.

Three-dimensional memory device including split memory cells and methods of forming the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel. Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure.

Three-dimensional memory device with drain-select-level isolation structures and method of making the same

Memory openings and backside openings are formed through an alternating stack of insulating layers and sacrificial material layers with patterned stepped surfaces and an overlying retro-stepped dielectric material portion. The backside openings may be formed in rows with shape modifications in staircase regions to provide more lateral elongation in areas with lesser layers of the alternating stack. Non-circular horizontal cross-sectional shapes for the backside openings in the staircase regions allow formation of the backside opening with less shape distortion. Memory opening fill structures are formed in the memory openings, and the sacrificial material layers are replaced with electrically conductive layers using the backside openings as conduits for an etchant and for a deposition precursor material. The electrically conductive layers are isotropically recessed around each backside opening to form width-modulated cavities, which is filled with width-modulated insulating wall structures.

Three-dimensional memory device having double-width staircase regions and methods of manufacturing the same

An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same

Memory openings and backside openings are formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. Memory opening fill structures are formed in the memory openings, and sacrificial backside opening fill structures are formed in the backside openings. Cavities are formed in volumes of the backside openings by removing the sacrificial backside opening fill structures. Remaining portions of the sacrificial material layers are replaced with material portions including electrically conductive layers. Each electrically conductive layer is formed as a continuous material layer including holes around the backside openings. Each electrically conductive layer is singulated into a plurality of electrically conductive strips by isotropically recessing the electrically conductive layers around each backside opening. Width-modulated cavities including expanded volumes of the backside openings are formed, and are filled with width-modulated insulating wall structures.

Three-dimensional memory device employing discrete backside openings and methods of making the same

Memory opening fill structures extend through an alternating stack of insulating layers and electrically conductive layers and a combination of an insulating fill material layer and plate electrode portions located over the alternating stack. Each memory opening fill structure includes a memory film, a vertical semiconductor channel laterally surrounded by the memory film, and a tubular electrode portion overlying the alternating stack and contacting a respective one of the plate electrode portions. The insulating fill material layer includes a drain select level isolation structure located between neighboring rows of memory opening fill structures. The plate electrode portions and the tubular electrode portions collectively constitute drain select gate electrodes. The tubular electrode portions are incorporated into a respective memory opening fill structure, and the drain select level isolation structure can be self-aligned to the memory opening fill structures.

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Yokkaichi, Japan

Takaaki Iwai