Hitachi, Ltd.

Other

Hitachi Vlsi Engineering Corp.

Hitachi Microcomputer Engineering, Ltd.

Takaaki Hagiwara

Yuji Yatsuda

Shinichi Minami

Ryuji Kondo

Yokichi Itoh

Hitoshi Kume

Satoshi Meguro

Hideaki Yamamoto

Kazuhiro Komori

Toshihisa Tsukada

Toru Kaga

Masatada Horiuchi

Tadashi Muto

Akihiro Shimizu

Takeshi Wada

Yoshiaki Kamigaki

Tetsuo Adachi

Toshiaki Nishimoto

Yoshimune Hagiwara

Hiroo Masuda

Atsushi Takai

Terumi Sawase

Yasurou Kubota

Kazuyoshi Shoji

Yuzo Kita

Kiyofumi Uchibori

Kazuto Izawa

Yasuo Igura

Toshiko Koizumi

Shun-ichi Saeki

Shin-ichi Minami

Yuko Nabetani

Toshihisa Tsukuda

This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.

Method of making an EPROM with peripheral transistor

The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.

Semiconductor device having aligned semiconductor regions and a

Method of manufacturing a semiconductor device

Semiconductor device and method for manufacturing the same

Method of manufacturing EEPROM memory device

Method for manufacturing a semiconductor device

This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.

Semiconductor memory device

Method for manufacturing field effect transistors

A time circuit is provided for a nonvolatile memory device which can electrically be written into. When the write operation on a particular memory cell lasting a relatively long period of time is specified from an external device, the memory device stops the write operation on that memory cell, irrespective of the external write operaiton specification, when the time set on the timer circuit has elapsed. The nonvolatile memory device has memory cells, each consisting of a single transistor. The erase operation on the memory cells is controlled according to a current flowing through these memory cells.

Nonvolatile semiconductor memory device

An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.

Method of forming well regions for field effect transistors utilizing

In a semiconductor device which includes an insulation film through which a charge can tunnel, a gate insulation film of a material different from the material of said insulation film or having a thickness different from that of said insulation film, and a floating gate extending over said tunnelable insulation film, the improvement wherein at least two sides of said tunnelable region are bounded by a device separation oxide film.

Semiconductor device

In a semiconductor memory made up of semiconductor memory elements, each consisting of a transistor of an MOS structure which has a charge-storage layer and which is formed on a semiconductor substrate, the improvement wherein a switching element is provided so that positive or negative charge can be stored or discharged from the charge-storage layer in a mode for writing data, and the charge-storage layer can be allowed to float electrically when in a mode for reading data.

Electrically erasable programmable RAM

A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal-silicon nitride-silicon dioxide-semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal-silicon dioxide-semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.

Nonvolatile semiconductor memory

Growing community of inventors

Stanford, CA, United States of America

Takaaki Hagiwara