Fujitsu Corporation

Spansion Llc.

Fujitsu Vlsi Limited

Takaaki Furuyama

Satoru Kawamoto

Shozo Kawabata

Mitsuhiro Nagao

Masahiro Niimi

Kenji Shibata

Makoto Niimi

Yoshihiro Takemae

Kenji Nagai

Yasuharu Satoh

Yukinori Kodama

Masaya Katayama

Hiroyuki Sugamoto

Kenta Kato

Koji Shimbayashi

Akira Sugiura

Yukihiro Nomura

Masaki Ito

Hajime Sato

Hirohiko Mochizuki

Kazufumi Komura

Hidenori Nomura

Tsuyoshi Ohira

Yasuhiro Yamamoto

Satoru Sugimoto

Meiko Kobayashi

A nonvolatile memory devicecapable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory deviceis provided with a plurality of banks, a rewrite control unitto which a first power source line VCCand a first ground line VSSare connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unitto which a second power source line VCCand a second ground line VSSare connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unitand the read control unitare arranged so as to be spaced from each another.

Nonvolatile memory device having a plurality of memory blocks

In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.

Time reduction of address setup/hold time for semiconductor memory

A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.

Method and apparatus for address allotting and verification in a semiconductor device

The semiconductor device comprises a first wellof a first conduction type formed in a semiconductor substrate; a second wellof a second conduction type formed in the first well; and a transistorincluding a control gateformed of an impurity region of the first conduction type formed in the second well, a first impurity diffused layerand a second impurity diffused layerformed with a channel regiontherebetween, and a floating gate electrodeformed on the channel regionand the control gatewith a gate insulation filmtherebetween. The control gateis buried in the semiconductor substrate, which makes it unnecessary to form the control gateon the floating gate electrode. Thus, the memory transistor and the other transistors, etc. can be formed by the same fabricating process. Thus, the fabrication processes can be less and the semiconductor device can be inexpensive.

Method for fabricating a semiconductor device

When an initializing operation starts, a busy state indicative of the disenable of access operation is set (S), and read operation information is read out by preferentially using a verify sense amplifieror a high-speed read sense amplifier(S). Upon completion of latching the read operation information (S: Y), a ready state that announces that the read access operation from a non-redundant memory region is enabled is set (S), and a ready signal is outputted according to an external read access request to the non-redundant memory region. A boot program or the like which is in the non-redundant memory region can be read out in parallel with the read of the operation information. Subsequently, the redundancy information is read out (S), and a ready state that announces that the read access operation from all of the memory regions is enabled is set upon completion of reading out the redundancy information (S). Thereafter, rewrite operation information is read out (S). The period of time since the start of the initializing operation to the start of the read access operation can thereby be reduced.

Method and apparatus for initialization control in a non-volatile memory device

An access identification circuit () identifies a first access operation or a second access operation and outputs an identification signal S. During the first access operation, stored data is read out after detecting a column address CADD, a burst address, and updating a word line to newly select memory cells MC. In the second access operation, the memory cells MC connected to the common word line which has been selected are selected by sequentially switching column selector switches. Operating condition information Dx (DAx and/or DBx) used for setting a load condition in a dummy load circuit () and/or setting a pulse width for an equalize signal EQ in an amplification control circuit () is stored in each of first and second storage sections () that are provided for the first and second access operations, respectively. The operating condition information Dx is selected by a selector circuit () in response to the identification signal S and fed to the dummy load circuit () and/or the amplification control circuit (). A suitable operating condition is selected for each of the access operations.

Memory device and control method therefor

A memory system (A) includes a memory section (A) and a memory control section (A). The memory section (A) includes a test circuit (A), a data register (A), a data output section (A), and a memory core section (A). Data DI is held in the data resistor (A). The test circuit (A) outputs write inhibit signal WINH to the memory core section (A) in response to test signal TEST. Write instruction recognition signal WR which recognizes that a write command is inputted into the memory section (A) and select signal S are inverted and, in response thereto, retained data DR of the data register (A) is outputted as output data DO from the data output section (A). Thus, it is possible to test whether generation, propagation, or recognition operation of a write command CMD and the data DI is normal or not without executing the operation of writing data into a memory cell of the memory section.

Memory system and test method therefor

In Step, a bias is applied (ON) to all of vertical rows Z() to Z(). With respect to the horizontal rows, a bias is not applied (OFF) to a horizontal row Z() where the defective sector exists and a bias is applied (ON) to the other horizontal rows Z() and Z(). On the sectors in the horizontal rows Z() and Z(), a voltage stress is applied and an access operation is performed. In Step, with respect to the vertical rows, a bias is not applied (OFF) to a vertical row Z() where the defective sector exists and a bias is applied (ON) to the other vertical rows Z() and Z(). With respect to the horizontal rows, a bias is applied (ON) to the horizontal row Z() where the defective sector exists, and no bias is applied (OFF) to the other horizontal rows Z() and Z(). As for the two steps, a voltage stress can be applied once to the sectors other than the defective sector.

Method and apparatus for applying bias to a storage device

A non-volatile memory in which a plurality of memory cells connected to a same word line are entirely written with data. Source lines SL separated from each other in column units is arranged on each memory cell of a memory cell array. When writing data, one of either a first or a second source voltage is applied to each source line in accordance with data that is to be written. After a first control voltage of negative voltage is applied, a second control voltage of high voltage is applied to the word line with the voltage of each source line SL in a maintained state. Therefore, each memory cell is erased or programmed in accordance with the voltage applied to the respective source line.

Non-volatile memory and write method of the same

An address identifying memory block is match-compared with address information stored in a to-be-remedied block memory section in a block redundancy judge section. A redundant block select signal is outputted from the block redundancy judge section by judgment of address match. A memory block column select section selects a memory block column having a redundant memory block irrespective of an address signal as the redundant block select signal is activated if block redundancy is activated to output a memory block column select signal. A column redundancy memory section selects address information of column redundancy relating a redundant memory block arranged in a memory block column in accordance with the memory block column select signal.

Semiconductor memory storage device and a redundancy control method therefor

A semiconductor memory device includes a memory block having memory cells connected to global bit lines and global word lines are arranged in matrix constitutes a memory block column sharing global bit lines, the memory block column being developed in global word line wiring direction, wherein at least two of memory block columns adjoining each other constitute a to-be-remedied unit, and redundant block(s), which is/are arranged sharing global bit lines with the memory block column(s), which is/are provided in each to-be-remedied unit and number of redundant block(s) is/are smaller than that of memory block column(s) included in the to-be-remedied unit. A minimum number of redundant memory blocks necessary for defectiveness remedy can be provided thereby enhancing the yield with optimization of the manufacturing and circuits. Redundancy remedy efficiency can also be improved while minimizing increased chip die size of the semiconductor memory device.

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Kasugai, Japan

Takaaki Furuyama