Chartered Semiconductor Manufacturing Ltd (corporation)

Tak Yan Tse

Juan Boon Tan

Mei Sheng Zhou

Simon Yew-Meng Chooi

Fang Hong Gn

Sajan Marokkey Raphael

A method for checking the position of alignment marks after a chemical mechanical polishing (CMP) process and automatically compensating for alignment of a wafer stepper based on the position checking is described. A wafer is provided having an alignment mark thereon for the purpose of aligning a reticle in the wafer stepper. The wafer is polished by CMP. Thereafter, alignment mark positioning is checked for deviation from a normal vectorial position of the alignment mark whereby information about the deviation is fed back to the wafer stepper and wherein the wafer stepper automatically compensates for correctable alignment error based on the deviation information.

Accurate wafer patterning method for mass production

A method of removing excess metal, particularly copper, in the fabrication of interconnects has been achieved. In accordance with the objects of this invention, a new method of removing excess metal in the formation of an interconnect has been achieved. A semiconductor substrate is provided. A dielectric layer is provided overlying the semiconductor substrate. Trenches are formed in this dielectric layer for planned damascene or dual damascene interconnects. A barrier layer is provided overlying the dielectric layer and lining the trenches. A metal layer is provided overlying the barrier layer and completely filling the trenches. A masking layer is deposited overlying the metal layer. The masking layer is patterned to form a mask that only overlies the trenches. The metal layer is etched down where not covered by the mask. This etching down is partial so that the barrier layer is not exposed. This etching down leaves the metal layer underlying the mask thicker than the metal layer not underlying the mask. The masking layer is etched away. The metal layer and the barrier layer are polished down to the top surface of the dielectric layer to form the planned interconnects, and the integrated circuit is completed.

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Singapore, Singapore

Tak Yan Tse