Tdk Corporation

Taisuke Ahiko

Masaaki Togashi

Akitoshi Yoshii

Sunao Masuda

Takaya Ishigaki

Takashi Aoki

Hiroki Sato

Atsushi Takeda

Masanori Yamamoto

Shirou Ootsuki

Akira Goshima

Shinya Onodera

Takashi Kamiya

Osamu Honjyo

Kamiya Takashi

Takashi Chiba

Naruki Kataoka

Tomohiro Sogabe

Yasushi Izumibe

Hiromi Kikuchi

Tsuyoshi Takashima

Masumi Miyairi

Akio Kikuchi

Miki Kimura

Hiroki Houchi

Junichi Musaka

Hiroki Satoh

Tooru Suda

A method for mounting a chip component includes the steps of: flattening a solder deposit adhering onto a land terminal of a circuit board; forming grooves on the solder deposit simultaneously with or after flattening the solder deposit; coating the solder deposit with a flux; and placing a chip component on the solder deposit with the flux interposed therebetween.

Method for mounting chip component and circuit board

The present invention is an electronic component series, comprising a carrier tape which has a plurality of storage recesses cyclically arranged along the longitudinal direction, electronic components to be stored in the plurality of storage recesses, a cover tape established to cover the plurality of storage recesses of the carrier tape, and a pair of adhesive regions which adhere to the carrier tape and to the cover tape, and extend along the longitudinal direction of the carrier tape so as to enclose the plurality of storage recesses from both sides, wherein the adhesive width of the pair of adhesive regions is cyclically increased in size corresponding to the storage recesses respectively. With this electronic component series, the difference in the peel strength of the cover tape between the first adhesive regions and the second adhesive regions can be sufficiently reduced.

Electronic component series

A multilayer capacitor comprised of dielectric layers stacked to form a device body in which a plurality of first internal electrode layers and a plurality of second internal electrode layers formed in planar shapes are alternately arranged while being separated through the dielectric layers, wherein the first external electrodes and second external electrodes are arranged at only a first end face of the device body, lead use columnar electrodes connect the internal electrode layers stacked close to the first end face of the device body and external electrodes, interlayer connection use columnar electrodes connect the internal electrode layers stacked at the inside of the device body, and the interlayer connection use columnar electrodes have cross-sectional areas larger than the cross-sectional areas of the lead use columnar electrodes.

Multilayer capacitor

A chip type electronic component for test is provided with an element body, and four or more terminal electrodes placed on the exterior of the element body. The element body has a plurality of laminated insulator layers, and a plurality of internal electrodes arranged to be opposed to each other with the insulator layer in between. Each of the internal electrodes is connected to at least one same terminal electrode out of the four or more terminal electrodes and connected to any one terminal electrode except for the at least one same terminal electrode.

Chip type electronic component for test, and mounted state test method

A multilayer capacitor has a multilayer body in which multiple dielectric layers and multiple inner electrodes are alternately laminated, and multiple terminal electrodes formed on the multilayer body. The multiple inner electrodes include multiple first inner electrodes and multiple second inner electrodes alternately arranged. The multiple terminal electrodes include first and second terminal electrodes electrically insulated from each other. The multiple first inner electrodes are electrically connected to each other by way of a through-hole conductor. The multiple second inner electrodes are electrically connected to each other by way of a through-hole conductor.

Multilayer capacitor and method of adjusting equivalent series resistance of multilayer capacitor

An electronic component having an element body, and a terminal electrode disposed on the element body. The terminal electrode has a first electrode layer, a second electrode layer, and a third electrode layer. The first electrode layer is formed on an external surface of the element body and formed by baking of a conductive paste. The second electrode layer is formed by Ni plating on the first electrode layer. The third electrode layer is formed by Sn plating or Sn alloy plating on the second electrode layer. A thickness of the second electrode layer is set in a range of not less than 5 &#x3bc;m, and less than 8 &#x3bc;m.

Electronic component and electronic device

A laminated capacitor includes: a dielectric body; first terminal electrodes arranged at intervals on one surface of the dielectric body; second terminal electrodes arranged at intervals on the surface of the dielectric body; first internal electrodes arranged in layers within the dielectric body; second internal electrodes arranged in layers within the dielectric body to alternate with the first internal electrodes; first outer through-hole conductors each connecting each first terminal electrode to one first internal electrode which is located closest to the surface of the dielectric body among the first internal electrodes; second outer through-hole conductors each connecting each second terminal electrode to one second internal electrode which is located closest to the surface of the dielectric body among the second internal electrodes; a first inner through-hole conductor connecting the first internal electrodes to one another; and a second inner through-hole conductor connecting the second internal electrodes to one another.

Laminated capacitor and manufacturing method thereof

A multilayer capacitor comprises a ceramic sintered body, an internal electrode disposed in the ceramic sintered body, and an external electrode disposed on an external surface of the ceramic sintered body. The external electrode has a first electrode layer formed on the external surface of the ceramic sintered body, a second electrode layer formed on the first electrode layer, and a conductive resin layer formed on the second electrode layer. The internal electrode and the first electrode layer consist primarily of a base metal. The second electrode layer consists primarily of a noble metal or a noble metal alloy. The conductive resin layer contains a noble metal or a noble metal alloy as a conductive material.

Ceramic electronic component and multilayer capacitor

A multilayer capacitor includes a multilayer body in which dielectric layers and inner electrodes are alternately laminated, and terminal electrodes formed on the multilayer body. The inner electrodes include first inner electrodes and second inner electrodes alternately arranged. The terminal electrodes include at least three terminal electrodes. The first inner electrodes are electrically connected to each other via a through-hole conductor. The second inner electrodes are electrically connected to each other via a through-hole conductor. At least two first inner electrodes in the first inner electrodes are electrically connected via a lead conductor to at least two respective terminal electrodes whose number is smaller than the total number of the terminal electrodes by at least 1 in the at least three terminal electrodes. At least one second inner electrode in the second inner electrodes is electrically connected via a lead conductor to the remainder of terminal electrodes other than the terminal electrodes electrically connected to the first inner electrodes via the lead conductor. An equivalent series resistance is set to a desirable value by adjusting the number of at least one species of the first and second inner electrodes electrically connected to the terminal electrodes via the lead conductors.

A first inner conductor, a second inner conductor, a first inner conductor, and a second inner conductor are disposed in the order mentioned from the top in the dielectric element. The first inner conductors are respectively led out to two opposing side surfaces of the dielectric element. A pair of the second inner conductors is respectively led out to two opposing side surfaces different from the two opposing side surfaces to which the first inner conductors are respectively led out. Terminal electrodes are respectively disposed on four side surfaces of the dielectric element for connection with these four inner conductors respectively.

A chip-type electronic component comprises a chip element body including an inner circuit element, and a pair of terminal electrodes electrically connected to the inner circuit element. The pair of terminal electrodes are positioned at respective end portions of the chip element body. The chip element body has one side face acting as a mounting surface opposing a circuit substrate. The pair of terminal electrodes include an electrode portion formed on the mounting surface. Here, it is assumed that a first direction is a direction orthogonal to the mounting surface, a second direction is a direction along which the pair of terminal electrodes oppose each other on the mounting surface, and a third direction is a direction orthogonal to the first and second directions. A first length of the electrode portion along the second direction from an edge portion of the mounting surface at a center region in the third direction is set longer than a second length of the electrode portion along the second direction from the edge portion of the mounting surface at both end regions in the third direction.

Chip-type electronic component

A multilayer capacitor comprises a multilayer body and a plurality of terminal electrodes formed on the multilayer body. The plurality of terminal electrodes include first and second terminal electrodes. The multilayer body is constructed by alternately laminating a plurality of dielectric layers and first and second inner electrode layers. The first inner electrode layer includes a first lead electrode electrically connected to the first terminal electrode and a first capacitor electrode forming a capacitance component. The portion positioned between a pair of slits provided in the first capacitor electrode is continuous with the first lead electrode. The second inner electrode layer includes a second lead electrode electrically connected to the second terminal electrode and a second capacitor electrode forming a capacitance component. The portion positioned between a pair of slits provided in the second capacitor electrode is continuous with the second lead electrode.

A first inner conductor (), a second inner conductor (), a first inner conductor (), and a second inner conductor () are disposed in the order mentioned from the top in the dielectric element (). The first inner conductors () are respectively led out to two opposing side surfaces of the dielectric element. A pair of the second inner conductors () is respectively led out to two opposing side surfaces different from the two opposing side surfaces to which the first inner conductors () are respectively led out. Terminal electrodes () are respectively disposed on four side surfaces of the dielectric element () for connection with these four inner conductors () respectively.

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Nikaho, Japan

Taisuke Ahiko