Fujitsu Semiconductor Limited

Fujitsu Corporation

Socionext Inc.

Fujitsu Microelectronics Limited

Taiki Uemura

Yoshiharu Tosaka

Seiki Sakuyama

Takayuki Shibasaki

Kozo Shimizu

Taiji Sakai

Hideki Kitada

Toshiyuki Miyazawa

A device including: defining unit to define lattice space that is collection of lattices compound groups are sequentially arranged; limiting unit to, in the case where any of the compound groups is arranged in any of the lattices of lattice space followed by arranging next compound group in the lattice space, generate limited lattice space created by eliminating, from the lattice space, undesirable regions for the next compound group to be arranged; and assigning unit to assign bit to each of lattice points, to which the compound groups can be arranged, in the limited lattice space; and an arithmetic unit configured to perform ground state search on Ising model obtained through conversion based on restriction conditions related to each lattice point according to simulated annealing, to calculate minimum energy of the Ising model, wherein the device is for searching compound in which the compound groups are linked with one another.

Device and method for searching compound

An optimization apparatus includes a memory; and a processor coupled to the memory and the processor configured to: compute a local solution for a combinatorial optimization problem based on a first evaluation function representing the combinatorial optimization problem, select a state variable group targeted by partial problems from the plurality of state variables based on a first state variable whose value at the local solution is a predetermined value among the plurality of state variables included in the first evaluation function, a weight coefficient representing a magnitude of an interaction between the plurality of state variables held in a storage unit, and input selection region information, search a ground state for a second evaluation function representing the partial problems for the selected state variable group, and generate a whole solution by updating the local solution based on the partial solutions acquired by the ground state search.

Optimization apparatus, control method for optimization apparatus, and recording medium

An electronic device includes: a first layer that includes first electronic components in a group and has a first through space between adjacent ones of the first electronic components; and a second layer that is stacked over the first layer and includes second electronic components which are coupled to the first electronic components and a second through space between adjacent ones of the second electronic components, the second through space being partially overlapping with the first through space.

Electronic device, method of manufacturing electronic device, and electronic apparatus

An electronic apparatus includes a first circuit board, a stacked circuit that is provided on the first circuit board through first coupling terminals and has a structure in which arithmetic elements and memory elements are stacked through inter-element coupling terminals and to which a signal is inputted from the first circuit board, and a second circuit board that is provided on the stacked circuit through second coupling terminals and to which a result of processing is outputted from the stacked circuit, wherein a number of the first coupling terminals and a number of the second coupling terminals are smaller than that of the inter-element coupling terminals.

Electronic apparatus, fabrication method therefor and electronic part

An electronic apparatus includes: a first electronic component including a first electrode; solder on the first electrode; and a phase containing In, Ag, and Cu, the phase being dispersed and included in the solder. And a method for manufacturing an electronic apparatus, the method includes: forming solder on a first electrode of a first component, the solder including a phase containing In, Ag, and Cu, the phase being dispersed in the solder.

Electronic apparatus and method for manufacturing the same

An electronic device includes an electrode including Cu, a solder including Sn and provided above the electrode, and a joining layer including In and Ag and provided along a boundary between the electrode and the solder. The joining layer including In and Ag prevents Cu&#x2014;Sn alloy, such as CuSn, from being formed at the boundary between the electrode and the solder, and prevents generation of voids and cracks resulting from the Cu&#x2014;Sn alloy. The electrode and the solder are joined with sufficient strength by the joining layer.

Electronic device and electronic apparatus

An electronic device includes a first electronic part, a second electronic part opposite the first electronic part, and a bonding portion between the first electronic part and the second electronic part. The bonding portion contains a solder containing a substance whose crystal structure reversibly changes in temperature rise and fall processes which accompany the operation of the electronic device or electronic equipment including the electronic device. A change in the crystal structure of the substance contained in the solder promotes recovery and recrystallization of the solder in the temperature rise and fall processes which accompany the operation of the electronic device or the electronic equipment. As a result, the coarsening of crystal grains in the solder is suppressed.

Electronic device, electronic part, and solder

An electrical apparatus includes a first electrical component; a second electrical component; and an In&#x2014;Sn&#x2014;Ag alloy connecting the first electrical component and the second electrical component, the In&#x2014;Sn&#x2014;Ag alloy containing AgInand AgIn, a AgIn content being lower than a AgIncontent.

Electrical apparatus

There is provided a semiconductor device having: a latch circuit having a plurality of data holding nodes; a first capacitance element connected to the first data holding node included in the plurality of data holding nodes; and a first switch element provided between the first data holding node and the first capacitance element.

Semiconductor device

There is provided a semiconductor device having: a latch circuit () having a plurality of data holding nodes; a first capacitance element (C) connected to the first data holding node (A) included in the plurality of data holding nodes; and a first switch element (SW) provided between the first data holding node (A) and the first capacitance element (C).

A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.

Latch circuit

A semiconductor device has a first latch circuit, a second latch circuit configured to receive an output of the first latch circuit, a first switching element provided between the first latch circuit and the second latch circuit, a feedback line for feeding data held by the second latch circuit to the first latch circuit, and a second switching element provided on the feedback line.

A CAD device according to the embodiments includes means that determines signal transmission time of each signal transmission circuit in an LSI circuit, means that determines an output inversion rate of a flip-flop circuit included in each signal transmission circuit when the flip-flop circuit is exposed to radiation, means that determines a signal transmission circuit that is a critical path, means that calculates a total soft error rate of the LSI circuit on the basis of the signal transmission time, the output inversion rate, and a clock period, and means that, when a predetermined soft error rate is less than the total soft error rate of the LSI circuit as a result of comparison, reducing the total soft error rate of the LSI circuit to the extent possible without changing signal transmission time of the signal transmission circuit, which is a critical path.

Signal transmission circuit for increasing soft error tolerance

A semiconductor device includes: a first master-slave flip-flop having a first master latch which receives and latches first data signal in synchronism with first clock and a first slave latch which receives and latches the first data signal from the first master latch in synchronism with second clock; and a second master-slave flip-flop disposed side by side with the first master-slave flip-flop and having a second master latch which receives and latches second data signal in synchronism with third clock and a second slave latch which receives and latches the second data signal from the second master latch in synchronism with fourth clock, and wherein the second slave latch of the second master-slave flip-flop is disposed adjacent to the first master latch of the first master-slave flip-flop and the second master latch of the second master-slave flip-flop is disposed adjacent to the first slave latch of the first master-slave flip-flop.

In a random access memory, one of a first conductivity type well constituting a first bit in one column group and another first conductivity type well constituting a second bit selected simultaneously to the first bit in an adjacent column group, is isolated from a common well of the first conductivity type by providing a deep well of a second conductivity type, such that the area of the deep well of the second conductivity type does not exceed the area of one column group.

Growing community of inventors

Kawasaki, Japan

Taiki Uemura