Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Panasonic Corporation

Matsushita Electronics Corporation

Taiji Noda

Yoshihiro Sato

Shinji Odanaka

Satoshi Shibata

Hiroyuki Umimoto

Ryota Sakaida

Takayoshi Yamada

An imaging device includes a pixel region including an amplifying transistor that includes a first gate and that outputs a signal voltage corresponding to an amount of signal charge, a first peripheral region including at least one first peripheral transistor including a second gate, the first peripheral region being located outside the pixel region, and a semiconductor substrate provided with the amplifying transistor and the at least one first peripheral transistor. A gate length of the second gate is shorter than a gate length of the first gate. When at least one type of impurity that contributes to suppression of transient enhanced diffusion of a conductive impurity is defined as a first specific species, the at least one first peripheral transistor includes a first specific layer located in the semiconductor substrate, the first specific layer containing a conductive impurity and the first specific species.

Imaging device

An imaging device includes a semiconductor substrate and pixels, which includes a first pixel and second pixels adjacent thereto. Each of the pixels includes a first photoelectric conversion layer, a first pixel electrode, a first plug that electrically connects the semiconductor substrate and the first pixel electrode, a second photoelectric conversion layer, a second pixel electrode, and a second plug that electrically connects the semiconductor substrate and the second pixel electrode. In the first pixel and the plurality of second pixels, a distance between the closest plugs of the first plugs and the second plugs is larger than or equal to one-half of a pixel pitch, when viewed in a normal direction of the semiconductor substrate.

An imaging device includes: a semiconductor substrate including a first impurity region and a second impurity region; a first insulating layer on a portion of a surface of the semiconductor substrate; a second insulating layer on another portion of the surface of the semiconductor substrate, a thickness of the first insulating layer being greater than a thickness of the second insulating layer; a first transistor including: a first gate electrode facing the surface of the semiconductor substrate via the first insulating layer; the first impurity region as one of a source and a drain; and the second impurity region as the other of the source and the drain; and a photoelectric converter electrically connected to the first impurity region. The first insulating layer covers the first impurity region, and the second insulating layer covers the second impurity region.

Imaging device and manufacturing method thereof

An imaging device includes: a semiconductor substrate; a first insulating layer covering a surface of the semiconductor substrate, the first insulating layer including first and second portions, a thickness of the first portion being greater than a thickness of the second portion; and an imaging cell. The imaging cell includes: a first transistor including a first gate insulating layer and an impurity region in the semiconductor substrate as one of a source and a drain; a second transistor including a gate electrode and a second gate insulating layer; and a photoelectric converter electrically connected to the gate electrode and the impurity region. The first portion covers a portion of the impurity region, the portion being exposed to the surface of the semiconductor substrate. The first gate insulating layer is a part of the first portion. The second gate insulating layer is a part of the second portion.

A semiconductor device includes a gate electrode provided on a semiconductor region with a gate insulating film being interposed therebetween, extension diffusion layers provided in regions on both sides of the gate electrode of the semiconductor region, a first-conductivity type first impurity being diffused in the extension diffusion layers, and source and drain diffusion layers provided in regions farther outside than the respective extension diffusion layers of the semiconductor region and having junction depths deeper than the respective extension diffusion layers. At least one of the extension diffusion layers on both sides of the gate electrode contains carbon.

Semiconductor device

The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in the semiconductor region beneath the gate electrode. The channel doped layer contains carbon as an impurity.

Semiconductor device with carbon-containing region

A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and n-type diffused source and drain layers formed in regions of the semiconductor substrate located below both sides of the gate electrode. Insides of the n-type diffused source and drain layers are formed with p-type impurity implanted regions having a lower p-type impurity concentration than the impurity concentration of the n-type diffused source and drain layer.

Semiconductor device having halo implanting regions

Into a channel formation region of a semiconductor substrate of p-type silicon, indium ions are implanted at an implantation energy of about 70 keV and a dose of about 5&#xd7;10/cm, thereby forming a p-doped channel layer. Next, germanium ions are implanted into the upper portion of the semiconductor substrate at an implantation energy of about 250 keV and a dose of about 1&#xd7;10/cm, thereby forming an amorphous layer in a region of the semiconductor substrate deeper than the p-doped channel layer.

Semiconductor device and method for fabricating the same

An n-type channel diffused layer and an n-type well diffused layer are formed in the top portion of a semiconductor substrate, and a gate insulating film and a gate electrode are formed on the semiconductor substrate. Using the gate electrode as a mask, boron and arsenic are implanted to form p-type extension implanted layers and n-type pocket impurity implanted layers. Fluorine is then implanted using the gate electrode as a mask to form fluorine implanted layers. The resultant semiconductor substrate is subjected to rapid thermal annealing, forming p-type high-density extension diffused layers and n-type pocket diffused layers. Sidewalls and p-type high-density source/drain diffused layers are then formed.

Semiconductor device and fabrication method therefor

A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is formed in part of the semiconductor region beside the gate electrode through diffusion of a first dopant. A pocket dopant diffused layer of a second conductivity type is formed under the extended high-concentration dopant diffused layer through diffusion of heavy ions. The pocket dopant diffused layer includes a segregated part that has been formed through segregation of the heavy ions.

Method for fabricating a semiconductor device having a pocket dopant diffused layer

A semiconductor device includes a gate electrode formed on a semiconductor region via a gate insulative film and an extension high concentration diffusion layer of a first conductivity type formed in the semiconductor region beside the gate electrode. A dislocation loop defect layer is formed in a region of the semiconductor region beside the gate electrode and at a position shallower than an implantation projected range of the extension high concentration diffusion layer.

Semiconductor device and method for manufacturing the same

Between a source/drain heavily-doped diffusion layer and a region below a side face of a gate electrode in an epitaxial semiconductor substrate, an extension heavily-doped diffusion layer where N-type As ions are diffused is formed to have shallower junction than the source/drain heavily-doped diffusion layer. A pocket heavily-doped diffusion layer where P-type indium ions, that is, heavy ions having a relatively large mass number, are diffused is formed under the extension heavily-doped diffusion layer.

Semiconductor device having diffusion layer formed using dopant of large mass number

As impurity ions for forming a channel, heavy ions are implanted multiple times at a dose such that no dislocation-loop defect layer is caused to be formed, and an annealing process is performed after each ion implantation process has been carried out, thereby forming a heavily doped channel layer having a steep retro-grade impurity profile.

Method for fabricating semiconductor device

After a gate electrode has been formed over a semiconductor region with a gate insulating film interposed therebetween, an amorphous layer is formed in the semiconductor region by implanting heavy ions with a large mass into the semiconductor region using the gate electrode as a mask. Then, ions of a first dopant are implanted into the semiconductor region using the gate electrode as a mask. Next, a first annealing process is conducted on the semiconductor region at a temperature between 400&deg; C. and 550&deg; C., thereby making the amorphous layer recover into a crystalline layer. Subsequently, a second annealing process is conducted on the semiconductor region, thereby forming an extended high-concentration dopant diffused layer of a first conductivity type and a pocket dopant diffused layer of a second conductivity type. The extended high-concentration dopant diffused layer is formed to have a shallow junction by diffusing the first dopant, while the pocket dopant diffused layer is formed under the extended high-concentration dopant diffused layer by diffusing the heavy ions.

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Osaka, Japan

Taiji Noda