Mitsubishi Denki Kabushiki Kaisha

Taiji Imazu

Satoshi Matsumoto

Kazuharu Nishitani

Masao Takiguchi

In order to obtain an output circuit having pulldown resistance which feeds no through current to a CMOS inverter even if output impedance of a front stage circuit is in an extremely high state, an input end and an output end of an inverter (G1) are connected to an input terminal (P.sub.i) and a first input end of an OR gate (G5) respectively. A pulse generation circuit (SG) and a gate of a pulldown transistor (Q.sub.1) are connected to a second input end and an output end of the OR gate (G5) respectively. The pulldown transistor (Q.sub.1) has a drain and a source which are connected to the input terminal (P.sub.i) and a power source (V.sub.SS) respectively. An input end of a CMOS inverter (11) is connected to the input terminal (P.sub.i). Even if the front stage output impedance is extremely increased after the potential of the input terminal (P.sub.i) has been at a high logical level, the pulldown transistor (Q.sub.1) is quickly driven by pulses generated by the pulse generation circuit (SG), to lower the potential of the input end of the inverter (11).

Pulldown resistance control input circuit and output circuit

In order to obtain an output circuit having pullup resistance which feeds no through current to a CMOS inverter even if output impedance of a front stage circuit is in an extremely high state, an input end and an output end of an inverter (G1) are connected to an input terminal (P.sub.i) and a first input end of an AND gate (G5) respectively. A pulse generation circuit (SG) and a gate of a pullup transistor (Q.sub.1) are connected to a second input end and an output end of the AND gate (G5) respectively. The pullup transistor (Q.sub.1) has a drain and a source which are connected to the input terminal (P.sub.i) and a power source (V.sub.DD) respectively. An input end of a CMOS inverter (11) is connected to the input terminal (P.sub.i). Even if the front stage output impedance is extremely increased after the potential of the input terminal (P.sub.i) has been at a low logical level, the pullup transistor (Q.sub.1) is quickly driven by pulses generated by the pulse generation circuit (SG), to increase the potential of the input end of the inverter (11).

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Taiji Imazu