Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Mie Fujitsu Semiconductor Limited

United Semiconductor Japan Co., Ltd.

Other

Fujitsu Vlsi Limited

Suvolta, Inc.

Kyushu Fujitsu Electronics Limited

Taiji Ema

Toru Anezaki

Hideyuki Kojima

Kazushi Fujita

Makoto Yasuda

Kazuo Itabashi

Tomohiko Tsutsumi

Mitsuaki Hori

Kazuhiro Mizutani

Tohru Anezaki

Masaya Katayama

Masao Taguchi

Hiroyuki Ogawa

Koichi Hashimoto

Toshimi Ikeda

Junichi Ariyoshi

Nobuhiro Misawa

Junji Oh

Yasunobu Torii

Kazutaka Yoshizawa

Tatsuji Araya

Kazuyuki Kumeno

Narumi Ohkawa

Masayoshi Asano

Junichi Mitani

Shinichiro Ikemasu

Toshio Taniguchi

Lucian Shifren

Yunlong Sun

Shinichiroh Ikemasu

Edward J Swenson

Thomas Willoughby Richardson

Shigetoshi Takeda

Tatsumi Tsutsui

Seiichi Suzuki

Takashi Yabu

Dai Kanai

Satoru Miyoshi

Kenichi Kanazawa

Takuya Moriki

Hedeyuki Kojima

Tadaaki Hayashi, Legal Representative

Itsuo Yanagita

Peter B Gillingham

Pushkar Ranade

Lance A Scudder

Hiroshi Nomura

Shinichi Nakagawa

Teymur Bakhishev

Dalong Zhao

Tatsuya Kajita

Takehide Shirato

Satoru Saitoh

Akihiro Usujima

Katsuaki Ookoshi

Michiari Kawano

Masaaki Higashitani

Kazunari Shirai

Urupattur C Sridharan

Masahiro Nakahara

Katsuyoshi Kobayashi

Hisatsugu Shirai

Masahiro Kuwamura

Tohru Kohno

Toshifumi Mori

Masao Hayashi

Koichi Masuda

Tamon Shinmoto

A semiconductor device is disclosed. A gate electrode is provided above a semiconductor substrate. A sidewall insulation film is provided to the gate electrode. Source and drain regions are provided in the substrate and contain first conductive impurities. A first semiconductor region is provided in the substrate, is on a source region side, and has a concentration of the first conductive impurities lower than the source region. A second semiconductor region is provided in the substrate, is on a drain region side, and has a concentration of the first conductive impurities lower than the drain and first semiconductor regions. A channel region is provided between the first and second semiconductor regions. A third semiconductor region is provided under the channel region, and includes second conductive impurities higher in concentration than the channel region. Information is stored by accumulating charges in the sidewall insulation film.

Semiconductor device and method for fabricating semiconductor device

A control circuit controls a column decoder and a row decoder to perform reprogramming where, before the count of reprogramming operations involving erasures, each targeting one of a plurality of memory cells included in a memory cell array, reaches a predetermined number, a first extent (e.g. a sub-block) including the targeted memory cell and being smaller than the entire extent of the memory cell array is used as the unit of reprogramming, and when the count of reprogramming operations reaches the predetermined number, a second extent (e.g. the memory cell array corresponding to one sector) including the targeted memory cell and being larger than the first extent is used as the unit of reprogramming, and resets the count of reprogramming operations each time it reaches the predetermined number.

Non-volatile semiconductor memory device and method for reprogramming thereof

A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration C. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration Clower than the concentration C. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration C. A sign of a TCR of the second polycrystalline silicon changes at the concentration C.

Method of fabricating semiconductor device having resistance elements

There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.

Semiconductor device

A semiconductor device includes a gate insulator layer above a semiconductor substrate, a gate electrode above the gate insulating layer, a sidewall insulator layer on sidewalls of the gate electrode and above the substrate, source and drain regions within the substrate on both sides of the gate electrode, a first region within the substrate below a part of the sidewall insulator layer closer to the source region and having an impurity concentration lower than the source region, a second region provided within the substrate below a part of the sidewall insulator layer closer to the drain region and having an impurity concentration lower than the drain region, a channel region provided within the substrate between the first and second regions, and a third region within the substrate below the channel region and including impurities of a different type and having an impurity concentration higher than the channel region.

Semiconductor device having resistance elements and fabrication method thereof

A semiconductor device includes first and second transistors connected to the same power supply. Each of the first and second transistors includes, under a channel region of a low concentration provided between a source region and a drain region of a first conductivity type, an impurity region of a second conductivity type having a higher concentration. The thickness of the gate insulating film in one of the first and second transistors is made larger than the thickness of the gate insulating film in the other one.

A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.

Semiconductor device and manufacturing method of semiconductor device

A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area.

Method of manufacturing semiconductor device reducing variation in thickness of silicon layer among semiconductor wafers

A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

Semiconductor device, semiconductor wafer and manufacturing method of semiconductor device

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Kawasaki, Japan

Taiji Ema