Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Panasonic Holdings Corporation

Taiji Akizuki

Hisashi Adachi

Tomoaki Maeda

Mitsuru Tanabe

Masahiko Sagisaka

Suguru Fujita

Junji Sato

Koichiro Tanaka

Noriaki Saito

Shigeki Nakamura

Naoki Adachi

Masashi Kobayashi

Takayuki Sotoyama

Takahiro Shima

Masaki Kanemaru

Kazuya Toki

Tomoyuki Kinpara

An antenna wireless device includes: antenna elements; feed ports respectively corresponding to the antenna elements; one or more detection ports each corresponding to some or all of the plurality of antenna elements; transceiver circuits respectively connected to feed ports; and one or more reference transceiver circuits each connected to a corresponding one or more of the one or more detection ports. For each antenna element, the transceiver circuit processes a first signal to generate a second signal, the second signal fed to the feed port is output to the reference transceiver circuit through the detection port, the reference transceiver circuit processes the second signal to generate a third signal, and detects an amplitude and phase deviation based on the first signal and the third signal, and the transceiver circuit adjusts a phase and an amplitude of a transmission signal based on the amplitude and phase deviation.

Antenna wireless device

A wireless communication device includes a baseband variable gain amplifier that amplifies a transmission baseband signal, a local variable gain amplifier that amplifies a local signal, a frequency-conversion circuit that mixes the amplified transmission baseband signal and the amplified local signal to carry out a frequency conversion into a transmission high-frequency signal, a first detector that detects a power of the transmission high-frequency signal, and a controller that controls at least one of a gain of the transmission baseband variable gain amplifier and a gain of the local variable gain amplifier on the basis of the detected power of the transmission high-frequency signal so that a power of the transmission high-frequency signal to be detected takes a predetermined value.

Wireless communication device and wireless communication system

A detection calibration circuit includes a first distributor distributing a high frequency input signal, an amplifier amplifying the first high frequency output signal of the first distributor, a second distributor distributing the amplified first high frequency output signal of the first distributor, a reference signal generator outputting a reference signal in accordance with a switchable reference voltage, a switcher selecting a third high frequency output signal of the second distributor or a reference signal of the reference signal generator and outputting the selected signal, a detector detecting the third high frequency output signal of the second distributor or the reference signal of the reference signal generator from the switcher, a sensitivity switcher adjusting a sensitivity for an output signal of the detector, and a calibration control circuit adjusting a detection gain of an input signal of the detector and an input-output sensitivity for an output signal of the detector.

Detection calibration circuit and transmission apparatus

A gain control circuit includes: a gain switching controller that changes the gains of a fundamental frequency amplifier and an N-multiplied frequency amplifier; and a detection voltage comparator that determines whether the operating state of an N-multiplier is a saturated operation or a linear operation. The detection voltage comparator determines the operating state of the N-multiplier by comparing an amount of change in a detection signal (first detection signal) representing a fundamental frequency signal with respect to an amount of change in the gain of the fundamental frequency amplifier with an amount of change in a detection signal (second detection signal) representing a high-frequency signal with respect to the amount of change in the gain of the fundamental frequency amplifier. The gain switching controller adjusts the gains of the fundamental frequency amplifier and the N-multiplied frequency amplifier on the basis of the operating state of the N-multiplier.

Output control circuit

A transformer (A) outputs differential signals of a positive phase signal (VoutAp) having phase &#x3b8;1+90&#xb0; and a negative phase signal (VoutAn) having phase &#x3b8;1&#x2212;90&#xb0;. A transformer (B) outputs differential signals of a positive phase signal (VoutBp) having phase &#x3b8;2+90&#xb0; and a negative phase signal (VoutBn) having phase &#x3b8;2&#x2212;90&#xb0;. An adding circuit () composes a pair of differential output signals, as signals corrected in phase error (&#x3b8;1&#x2212;&#x3b8;2) generated in the transformers (A,B), in a manner of summing up vectors of two pairs of the differential signals outputted from the transformers (A,B) for the positive phase signal and the negative phase signal, respectively.

Power distribution circuit

A balun converts a single-ended radio-frequency signal into differential signals. A differential matching circuit outputs a maximum-level positive-phase output signal at a lower or higher frequency than the center frequency and outputs a maximum-level reverse-phase output signal at a higher or lower frequency than the center frequency. An amplification circuit amplifies a positive-phase output signal and a reverse-phase output signal of the differential matching circuit. A mixing circuit converts the positive-phase output signal and the reverse-phase output signal that are output from the amplification circuit into intermediate-frequency signals using locally generated signals.

Mixing circuit

A reception signal processing devices includes a converter which converts an analog signal amplified by an amplifying section to a digital signal, switches respectively provided in post-stages of variable gain amplifiers of the amplifying section, a bypass switch section which sets to open and close a path in which outputs of the variable gain amplifiers go around the variable gain amplifiers of the post-stages and are inputted to the converter, a switch controller which controls the switches and the bypass switch section and a DC offset controller which sets a correction value of a DC offset in accordance with a gain set to the variable gain amplifier as an object to be corrected.

Reception signal processing device

An A/D conversion device generates a control clock signal having a cycle that is an integral multiple of a cycle of a reference clock signal. A shift voltage is generated which varies every cycle of the reference clock signal while the cycle of the control clock signal is taken as one cycle. An analog signal is offset by the shift voltage. The offset analog signal is converted to a digital signal every cycle of the reference clock signal. Outputs from the A/D converter are averaged every cycle of the control clock signal.

A/D conversion device

A clock signal generation apparatus containing variable delay devices for varying the delay time of two-phase clock signals used in a load circuit that uses non-overlap clock signals; a non-overlap detector for detecting a non-overlap time in the H-level zones of the two-phase clock signals and outputting a detection signal corresponding to the non-overlap time; and a control signal generation section for generating a control signal that is used to control the variable delay devices on the basis of the detection signal from the non-overlap detector, and capable of securely generating the two-phase clock signals having an optimal non-overlap time while absorbing fluctuations due to temperature characteristics, power supply voltage characteristics and individual differences in components.

Clock signal generation apparatus

A multibit quantizer is provided, at its input terminals, with a variable gain circuit and an offset addition circuit to perform tracking control in which for each sampling time, the level of an offset signal of the offset addition circuit is adjusted based on output digital data of an output processing circuit and the preceding control signal of an offset control circuit so that the quantizer operates without causing a saturation operation. As a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time.

Delta sigma A/D modulator

The present invention is intended to attain simplified circuit configuration and low current consumption in a discrete time amplifier circuit and an AD converter, to improve the convergence from the transient response state to the steady state of the amplifier circuit and to reduce noise and distortion owing to the variation in the output common-mode voltage. The discrete time amplifier circuit and the AD converter are provided with a switched-capacitor common-mode feedback (CMFB) circuit capable of detecting and feeding back the output common-mode voltage at every sampling timing in the case that the circuit operates at double sampling timing (every &#xbd; cycle).

Discrete time amplifier circuit and analong-digital converter

In a delta-sigma modulator circuit, an integrator integrates an input signal, and a quantization circuit quantizes the integrated signal with a predetermined quantization number, and outputs a quantization result signal. A DA converter circuit outputs an analog signal indicating a DA conversion result based on the quantization result signal. An oscillation detector circuit detects that the integrator is in an oscillation state based on the integrated signal, and outputting an oscillation detection signal. A reset circuit resets the integrator based on the oscillation detection signal.

Delta-sigma AD converter apparatus using delta-sigma modulator circuit provided with reset circuit resetting integrator

A transmitter according to the present invention is a transmitter conforming to the EER method, wherein a modulated signal is separated into phase and amplitude components, and the components are input to the high-frequency input terminal and the power supply voltage terminals of a high-frequency power amplifier. This transmitter comprises an amplitude delay corrector and a phase delay corrector capable of correcting delay time so that the phase and amplitude components are optimally synthesized using two or more stages of saturation-type amplifiers constituting the high-frequency power amplifier. With this configuration, a synthesis error can be reduced in each stage of the saturation-type amplifier, and distortion components in the output waveform can be reduced.

Transmitter

In a delta-sigma modulator including first and second subtractors, first and second integrators, a quantizer, and a DA converter, a first feedback circuit includes first charge holding circuits which hold charges of the analog signal from the DA converter for different sampling intervals, can change a feedback amount of the analog signal from the DA converter, and outputs the analog signal from each first charge holding circuits to the second subtractor. A second feedback circuit includes second charge holding circuits which hold charges of the analog signal from the second integrator for different sampling intervals, can change a feedback amount of the analog signal from the second integrator, and outputs an analog signal from each of the second charge holding circuits to the second subtractor. A controller switches an order of filter characteristic of the delta sigma modulator by changing feedback amounts of the first and second feedback circuits.

Delta-sigma modulator and DA converter apparatus including delta-sigma modulator changing order of filter

An A/D converter includes a first switched capacitor block that charges and holds charges by connecting each of a first group of capacitors to a single basic reference voltage at a first timing, and discharges each of the charges held by the first group of capacitors at a second timing, a second switched capacitor block that charges and holds each of the charges discharged by the first group of capacitors respectively in the second group of capacitors at the second timing, and converts each of the charges held by the second group of capacitors to a voltage and outputs the voltages at the first timing, and a quantizer that quantizes an analog input signal using the plurality of voltages output from the second switched capacitor block as reference voltages for each level. A plurality of reference voltages is generated from a single basic reference voltage, based on different amounts of charges held in the plurality of capacitors. A high SNR is obtained by supplying the reference voltages of a quantizer in a multi-bit A/D converter with high accuracy, and low power consumption operation is possible with simplified circuitry.

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Miyagi, Japan

Taiji Akizuki