Sony Corporation

Taichi Hirao

Hiroaki Sakaguchi

Hiroshi Yoshikawa

Masaaki Ishii

Hiroshi Kobayashi

Haruhisa Yamamoto

Koichi Hasegawa

Hitoshi Kai

Yousuke Morita

Katsuhiko Metsugi

Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage sectionof a cache memory holds a reference number fieldin addition to a tag address field, a valid field, and a dirty field. The reference number fieldis set in a data write, and the value thereof is decremented after each read access. When the value of the reference number fieldis changed from '1' to '0', the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.

Data transfer in a multiprocessor using a shared cache memory

A cache memory includes: a tag storage section in which one of a plurality of indexes, each index containing a plurality of tag addresses and one suspension-indicating section, is looked up by a first address portion of an accessed address; a data storage section; a tag control section configured to, when the suspension-indicating section contained in the looked-up index indicates suspension, allow access relevant to the accessed address to wait, and when the suspension-indicating section contained in the looked-up index indicates non-suspension, compare a second address portion different from the first address portion of the accessed address to each of the plurality of tag addresses contained in the looked-up index, and detects a tag address matched with the second address portion; and a data control section.

Cache memory, cache memory control unit, and method of controlling the cache memory

Cache memory and cache memory control unit

An instruction fetch apparatus is disclosed which includes: a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions belonging to a plurality of instruction sequences are placed sequentially; a change designation register configured to designate a change of an increment value on the program counter; an increment value register configured to hold the changed increment value; and an addition control section configured such that if the change designation register designates the change of the increment value on the program counter, then the addition control section increments the program counter based on the changed increment value held in the increment value register, the addition control section further incrementing the program counter by an instruction word length if the change designation register does not designate any change of the increment value on the program counter.

Instruction fetch apparatus, processor and program counter addition control method

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Tokyo, Japan

Taichi Hirao