Taiwan Semiconductor Manufacturing Comp. Ltd.

Tai-Yung Yu

Yu-Sheng Su

Jin-Lin Liang

Li-Te Hsu

Pin-Chia Su

Pin Chia Su

Shian Wei Mao

Bo-Wei Chou

Wen-Cheng Lien

Li Te Hsu

Chien-Chang Fang

Hui Mei Jao

Chien-Hua Li

Tzu-Min Lee

Jin Lin Liang

Shih Cheng Yeh

Ying-Jie Cai

Shih-Hsing Kao

Shin-Hsien Yang

Cheng-Long Tao

Methods for cleaning a wafer in semiconductor fabrication are provided. The method includes providing a wafer. The method further includes cleaning the wafer in a first cleaning cycle by supplying a cleaning solution and supplying a first washing liquid mixed with a purge gas in sequence. The method also includes cleaning the wafer in a second cleaning cycle by supplying the cleaning solution and a second washing liquid mixed with the purge gas in sequence. The second cleaning cycle is initiated after the first cleaning cycle is finished.

Multi-cycle wafer cleaning method

A method of forming a shallow trench isolation (STI) structure in a substrate includes forming a pad oxide layer over the substrate. The method includes forming a nitride-containing layer over the pad oxide layer, wherein the nitride-containing layer has a first thickness. The method further includes forming the STI structure extending through the nitride-containing layer, into the substrate. The STI structure has a height above a top surface of the pad oxide layer. The method includes establishing a correlation between the first thickness, the height of the STI structure above the top surface of the pad oxide layer, and an offset between the first thickness and the height of the STI structure above the top surface of the pad oxide layer. The method includes calculating the height of the STI structure above the pad oxide layer based on the correlation, and selectively removing a determined thickness of the STI structure.

Method of forming shallow trench isolation structure

An etchant for removing a porous low-k dielectric layer on a semiconductor substrate includes a hydrofluoric acid-based solvent, a dilating additive for dilating the pores in the porous low-k dielectric, and a passivating additive that forms a passivation layer at the interface between the low-k dielectric layer and the semiconductor substrate.

Silicon wafer reclamation process

A chemical processing bath and system used in semiconductor manufacturing utilizes a dynamic spiking model that essentially constantly monitors chemical concentration in the processing bath and adds fresh chemical on a regular basis to maintain chemical concentrations at desirable levels. Etch rates and etch selectivities are maintained at desirable levels and contamination from undesirable precipitation is avoided. The system and method automatically compare concentration levels to a plurality of control limits associated with various technologies and identify the technology or technologies that may undergo processing.

Method and system for improving wet chemical bath process stability and productivity in semiconductor manufacturing

By exposing a process control wafer having a porous low-k-dielectric layer thereon in an HF-based low-k dielectric etching solvent comprising a dilating additive and a passivating additive, the pores in the low-k dielectric layer are dilated some of which connect with one another to form one or more continuous channels extending through the thickness of the dielectric layer and allowing the HF-based solvent to reach down to the substrate. Then the passivating additive component of the HF-based etching solvent forms a passivation layer at the dielectric layer and the substrate interface that protects substrate from the HF-based etchant.

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Rende, Italy

Tai-Yung Yu