Industrial Technology Research Institute

Taiwan Semiconductor Manufacturing Comp. Ltd.

Tai-Yuan Wu

Ching-Chiun Wang

Heng-Yuan Lee

Pang-Shiu Chen

Frederick Chen

Yu-Sheng Chen

Yu-Chang Jong

Wei-Su Chen

Hung-Chih Chen

Yu-De Lin

Hengyuan Lee

Ren-Jyh Leu

Pei-Yi Gu

Kun-I Lee

Pang-Hsu Chen

A resistive random access memory and a method for fabricating the same are provided. The method includes forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a first top electrode sub-layer on the oxygen atom gettering layer; forming a second top electrode sub-layer on the first top electrode sub-layer, wherein the first top electrode sub-layer and the second top electrode sub-layer comprise a top electrode; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.

Resistive random access memory and method for fabricating the same

Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening.

Via structure, memory array structure, three-dimensional resistance memory and method of forming the same

A resistive random access memory and a method for fabricating the same are provided. The method includes providing a bottom electrode formed on a substrate. A metal oxide layer is formed on the bottom electrode. An oxygen atom gettering layer is formed on the metal oxide layer. A top electrode is formed on the oxygen atom gettering layer. The previous mentioned structure is subjected to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, thus leaving a plurality of oxygen vacancies of the metal oxide layer.

Resistive random access memory having metal oxide layer with oxygen vacancies and method for fabricating the same

A method for forming a capacitor in a dynamic random access memory, comprising steps of: providing a semiconductor substrate having at least a transistor, whereon an interlayer dielectric layer having at least a first plug is formed so that the first plug is connected to the drain of the transistor; depositing an etching stop layer on the first plug and the interlayer dielectric layer; depositing a first insulating layer on the etching stop layer; forming at least a second plug on the first insulating layer and the etching stop layer so that the second plug is connected to the first plug; depositing a second insulating layer on the first insulating layer and the second plug; forming at least a mold cavity in the second insulating layer so that the aperture of the mold cavity is larger than the diameter of the second plug and there is a deviation between the mold cavity and the second plug; removing the first insulating layer in the mold cavity until the etching stop layer; depositing a first electrode layer to cover the second insulating layer, a sidewall portion of the mold cavity, the second plug and the etching stop layer; removing the second insulating layer so that the first electrode layer forms a single open-ended cavity; and depositing a dielectric layer and a second electrode layer.

Method for forming capacitor in dynamic random access memory

A method for forming a clear code mark that is independent of backend planarization by adding an extra exposing step to the normal photolithography process is described. A layer to be patterned is provided on a substrate. A photoresist layer is coated overlying the layer to be patterned. The photoresist layer is first exposed through a code mask and second exposed through a patterning mask. The photoresist layer is developed to form a photoresist mask having a code mark pattern from the code mask and a device pattern from the patterning mask. The layer to be patterned is etched away where it is not covered by the photoresist mask to form simultaneously device structures and a code mark in the fabrication of an integrated circuit device.

Method to form code marks on mask ROM products

Correction of overlay shift of an epitaxial silicon layer deposited on a semiconductor wafer, and of post-epitaxial silicon layers subsequently deposited, is disclosed. When an epitaxial silicon layer of a given thickness is deposited, the zero mark coordinates for the deposition are shifted relative to alignment marks on the wafer by a distance based on the thickness of the layer. The distance is preferably proportional to the thickness of the epi layer. This prevents overlay shift of the epi layer. For post-epitaxial silicon layers subsequently deposited, preferably except for the first post-epi layer, a clear out process is initially performed to maintain the alignment marks on the semiconductor wafer. In this way, overlay shift, or misalignment, of the post-epi layers is also prevented.

Growing community of inventors

Taipei, Taiwan

Tai-Yuan Wu