Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Chen, Tai-yi

Tai-Yi Chen

Chung-Chieh Yang

Yung-Chow Peng

Chung-Ting Lu

Yung-Shun Chen

Chung-Peng Hsieh

Chih-chiang Chang

Yun-Ru Chen

Nai Chen Cheng

Chih-Chiang Chang

Shih-Tsung Lin

Tse-Hung Chen

Chi-Kuang Liu

Wen-Hsien Huang

A system for fabricating a semiconductor device includes one or more data processors configured to perform operations commanded by instructions stored in a non-transitory computer-readable medium. The instructions include receiving a layout including a plurality of elements, extracting parasitic values associated with the layout to generate a resistance and capacitance (RC) netlist, generating a modified RC netlist by adding element names of the elements of the layout to the RC netlist, performing a post-layout simulation on the modified RC netlist to determine whether the layout meets a predetermined specification, and fabricating a semiconductor device based on the layout when it is determined that the layout meets the predetermined specification. The RC netlist includes the extracted parasitic values. The modified RC netlist includes a netlist table storing the element names and the extracted parasitic values.

System and method for fabricating a semiconductor device

An integrated circuit structure includes a first capacitor structure, disposed in a first layer on a semiconductor substrate and comprising a plurality of capacitors; a second capacitor structure, adjacent to first capacitor structure in the first layer, wherein the second capacitor structure and the first capacitor structure are arranged as a strip-shaped structure; a first conductive plate, disposed at one end of the strip-shaped structure in the first layer; and a second conductive plate, disposed in a second layer on the semiconductor substrate over the strip-shaped structure and extending toward the other end of the strip-shaped structure from the one end of the strip-shaped structure.

Integrated circuit structure of capacitive device

An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Analog cells utilizing complementary mosfet pairs

Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.

Two-step charge-based capacitor measurement

A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; modifying a pillar density of the initial power delivery network repeatedly when the circuit design does not meet the predetermined specification until the circuit design meets the predetermined specification to generate a circuit layout of the integrated circuit; and performing a post-layout simulation to the circuit layout.

Generation of layout including power delivery network

A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; and adding at least one additional conductive pillar or at least one additional power rail in the initial power delivery network according to a relationship of a pillar density of the initial power delivery network and a maximum pillar density when the circuit design does not meet the predetermined specification.

Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

Capacitor structure with low capacitance

An integrated circuit structure includes a first conductive plate, a second conductive plate, a plurality of conductive lines, and a plurality of conductive vias. The first conductive plate is disposed in a first layer on a semiconductor substrate. The second conductive plate is disposed in a second layer on the semiconductor substrate. The plurality of conductive lines are disposed in the first layer for surrounding the first conductive plate. The plurality of conductive vias are arranged to couple the plurality of conductive lines to the second conductive plate. The second layer is different from the first layer, and the first conductive plate is physically separated from the second conductive plate, the plurality of conductive lines, and the plurality of conductive vias.

A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; and when the circuit design meets the predetermined specification, generating a power delivery network layout of the integrated circuit, and generating, after the power delivery network layout is generated, a circuit layout of the integrated circuit.

A needle-free connector including a guiding base, a connecting base, a valve member, and a seal member is provided. The guiding base has a conduit, and the conduit extends downward along an axial direction. The connecting base is disposed on the guiding base and has a screw portion and a passage running through the screw portion. A chamber is formed between the guiding base and the connecting base, and the conduit and the passage respectively communicate with the chamber along the axial direction. The valve member is disposed between the guiding base and the connecting base, and is movably located in the chamber. The seal member is disposed at an end of the valve member far away from the conduit, and the seal member and the valve member are adapted to be connected into a whole in a manufacturing process.

Needle-free connector

An integrated circuit structure includes: a first conductive plate disposed in a first layer on a semiconductor substrate; a second conductive plate disposed in a second layer on the semiconductor substrate; a plurality of conductive lines disposed in the first layer, for surrounding the first conductive plate; and a plurality of conductive vias arranged to couple the plurality of conductive lines to the second conductive plate; wherein the second layer is different from the first layer, and the first conductive plate is physically separated from the second conductive plate, the plurality of conductive lines, and the plurality of conductive vias.

Growing community of inventors

Hsinchu, Taiwan

Tai-Yi Chen