Samsung Electronics Co., Ltd.

Tai-song Jin

Do-Hyung Kim

Suk-jin Kim

Seung-Won Lee

Jin-Seok Lee

Won-Sub Kim

Dong-Hoon Yoo

Bernhard Egger

Hee-Jin Ahn

Min-Wook Ahn

Donghoon Yoo

Yoonseo Choi

Seung-won Lee

Sun-hwa Kim

Dong-kwan Suh

Jae-un Park

Young-chul Cho

Yen-Jo Han

Dong-Kwan Suh

Sang-suk Lee

Provided are a method and apparatus for processing a very long instruction word (VLIW) instruction. The method includes acquiring a calculation allocation instruction including information regarding whether the VLIW instructions are allocated to a plurality of slots; updating a database including the information regarding whether the VLIW instructions are allocated to the plurality of slots based on the acquired calculation allocation instruction; and allocating at least one VLIW instruction to each of the plurality of slots based on the updated database.

Method and device for allocating a VLIW instruction based on slot information stored in a database by a calculation allocation instruction

A method and apparatus for performing a simulation by using a plurality of N processors in parallel include dividing the simulation scenario into N parts to distribute a simulation scenario to each of the processors; performing a high-detail simulation by using a first processor to which a part that includes a beginning part of the divided simulation scenario is distributed, from among the N processors; performing a fast simulation by using each of N&#x2212;1 processors, other than the first processor; and performing a high-detail simulation based on a snapshot that is generated after the fast simulation is finished, by using each of the N&#x2212;1 processors.

Method of and apparatus for performing simulation using plurality of processors in parallel

A method of preventing a bank conflict in a memory includes determining processing timing of each of threads of function units to access a first memory bank in which occurrence of a bank conflict is expected, setting a variable latency of each of the threads for sequential access of the threads according to the determined processing timing, sequentially storing the threads in a data memory queue according to the determined processing timing, and performing an operation by allowing the threads stored in the data memory queue to sequentially access the first memory bank whenever the variable latency of each of the threads passes.

Method and apparatus for preventing bank conflict in memory

Provided are a method and an apparatus for controlling a register of a reconfigurable processor. The power of a register may be efficiently used by obtaining a command for each of a plurality of read ports of the register from a memory, obtaining activation information for each of the plurality of read ports from the obtained command, and determining an address value of each of the plurality of read ports on the basis of the obtained activation information.

Method and apparatus for controlling register of reconfigurable processor, and method and apparatus for creating command for controlling register of reconfigurable processor

Provided method includes storing a first cache snap shot including cache profiling information regarding a cache when a first process being executed by a cycle accurate simulator is terminated; storing a second cache snap shot including the cache profiling information on the cache when a second process is executed in the cycle accurate simulator; comparing the second cache snap shot of the second process and the first cache snap shot of the first process to readjust any one value of a cache hit value and a cache miss value which are present in the second cache snap shot of the second process; and correcting the cache profiling information which is stored in the first cache snap shot of the first process by reflecting the readjusted any one value of the cache hit value and the cache miss value present in the second cache snap shot of the second process.

Method and apparatus for correcting cache profiling information in multi-pass simulator

Provided is a method of managing a register port, the method including performing scheduling on register ports that are used during a plurality of cycles to enable performing of a calculation; encoding data of the register ports according to results of the scheduling, the encoding of the data including, with respect to data of one of the register ports that does not have a schedule during one of the plurality of cycles, equally encoding the data of the one register port during the one cycle with data of an adjacent cycle of the one register port, the adjacent cycle being adjacent to the one cycle; and transmitting results of the encoding to a device that includes the register ports.

Method and apparatus for managing register port

A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Optimizing configuration memory by sequentially mapping the generated configuration data by determining regular encoding is possible and functional units are the same in adjacent cycles

Selecting a memory mapping scheme by determining a number of functional units activated in each cycle of a loop based on analyzing parallelism of a loop

Optimizing configuration memory by sequentially mapping the generated configuration data into fields having different sizes by determining regular encoding is not possible

A scheduling apparatus for dynamically setting a size of a rotating register of a local register file during runtime ids provided. The scheduling apparatus may include a determiner configured to determine whether a non-rotating register of a central register file is sufficient to schedule a program loop; a selector configured to select at least one local register file to which a needed non-rotating register is allocated in response to a determination that the non-rotating register of a central register file has a size which is sufficient to loop a program loop; a scheduler configured to schedule a non-rotating register of the at least one selected local register file.

Scheduling apparatus and method of dynamically setting the size of a rotating register

Reconfigurable processor and method for optimizing configuration memory

A method for scheduling loop processing of a reconfigurable processor includes generating a dependence graph of instructions for the loop processing; mapping a first register file of the reconfigurable processor on an arrow indicating inter-iteration dependence on the dependence graph; and searching for schedules of the instructions based on the mapping result.

Method and apparatus for instruction scheduling using software pipelining

An instruction compressing apparatus and method for a parallel processing computer such as a very long instruction word (VLIW) computer, are provided. The instruction compressing apparatus includes a bundle code generating unit, an instruction compressing unit, and an instruction converting unit. The bundle code generating unit may generate a bundle code in response to an input of instructions to be compressed. The bundle code may indicate whether a current instruction group is terminated, and also whether an instruction group following the current instruction group is a no-operation (NOP) instruction group. The instruction compressing unit may remove a NOP instruction and/or a NOP instruction group from the input instructions according to the generated bundle code. The instruction converting unit may include the generated bundle code in the remaining instructions which have not been removed by the instruction compressing unit.

NOP instruction compressing apparatus and method in a VLIW machine

A reconfigurable array is provided. The reconfigurable array includes a Very Long Instruction Word (VLIW) mode and a Coarse-Grained Array (CGA) mode. When the VLIW mode is converted to the CGA mode, instead of sharing a central register file between the VLIW mode and the CGA mode, live data to be used in the CGA mode is copied from the central register file to local register files.

Analyzing data flow graph to detect data for copying from central register file to local register file used in different execution modes in reconfigurable processing array

Provided is a technique that is capable of efficiently compressing instructions by inserting instruction compression bits into valid instruction bundles and deleting no operation (NOP) instruction bundles. Accordingly, the number of instructions that can be parallel-processed in a processor may be increased.

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Seoul, South Korea

Tai-song Jin