Skhynix Inc.

Hynix Semiconductor Inc.

Tai Sik Shin

Jin Ha Hwang

Dong Shin Jo

Duck Ju Kim

Kwang Ho Baek

Dong Hyeon Ham

An electronic device is provided. A buffer circuit, having improved reliability according to the present disclosure, includes a pause detector and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a toggle state or a pause state. The output signal controller generates an output signal based on the input signal and controls a duty cycle of the output signal according to the pause signal.

Buffer circuit and operating method thereof

An electronic device is provided. A buffer circuit, performing an optimized operation according to the present disclosure, includes a pause detector, a toggle detector, and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a pause state. The toggle detector receives the input signal and the pause signal and generates a toggle signal which indicates whether the input signal is in a toggle state. The output signal controller generates an output signal which controls input buffer circuits according to the toggle signal.

Memory device and operating method thereof

A memory system includes a flash memory device including a first memory block group on which a least significant bit (LSB) program operation has been performed and a program operation on another bit has not been performed and a second memory block group on which both the LSB program operation and a most significant bit (MSB) program operation have been performed and a memory controller configured to check which of the first and second memory block groups a memory block selected for an LSB data read operation belongs to and set a level of a read voltage for the LSB data read operation of the selected memory block.

Memory system and method of operating the same

A method of operating a nonvolatile memory device includes reading data stored in a main cell and a flag cell using a first read voltage, the nonvolatile memory device comprising the main cell for storing data including a least significant bit (LSB) and a most significant bit (MSB), and the flag cell for determining a program state of the main cell, determining a program state of the main cell based on the data read from the flag cell, reading data stored in the main cell and the flag cell using a second read voltage if a MSB page program has been performed on the main cell, and reading data stored in the main cell using a third or a fourth read voltage based on the data read from the flag cell using the second read voltage, if a threshold voltage of the main cell shifts.

Growing community of inventors

Gyeonggi-do, South Korea

Tai Sik Shin