Sun Microsystems, Inc.

Tai Quan

Brian L Smith

James Ray Lewis

David C Banks

John C Schell

Teshager Tesfaye

Kin M Ho

Drew George Doblar

Jurgen M Schulz

Michael J Grubisich

Matthew J Tedone

Kenneth A Schmahl

In a computer system having a first repeater and a second repeater, the first repeater coupled to the second repeater by a bus, the first repeater operable to transmit a transaction and a control signal to the second repeater, a method, performed by the second repeater, of generating an error comprising: predicting, in a first cycle, that a transaction should be transmitted from the first repeater to the second repeater; determining if a control signal was received within a predetermined number of cycles of the first cycle; and if the control signal is not received within the predetermined number of cycles of the first cycle, then generating an error.

Method and apparatus for verifying consistency between a first address repeater and a second address repeater

A computer system including a first repeater and a second repeater that is coupled to the first repeater. The computer system also includes a third repeater that is coupled to the first repeater. The first repeater contains a first arbiter that arbitrates transactions between the first repeater and the second repeater and also arbitrates transactions between the first repeater and the third repeater. The second repeater receives transactions from the first repeater and contains a second arbiter that predicts receipt of transactions from the first repeater to the second repeater.

Method and apparatus for efficiently broadcasting transactions between a first address repeater and a second address repeater

A method of synchronizing arbiters. The method is performed by a computer system that has a first repeater, a second repeater that is coupled to the first repeater, and a third repeater that is coupled to the first repeater. The method includes: instructing the second repeater to cease issuing transactions to the first repeater; synchronizing an arbiter within the second repeater with an arbiter within the third repeater; instructing the second repeater to begin issuing transactions to the first repeater; and instructing the third repeater to begin issuing transactions to the first repeater.

Method of synchronizing arbiters within a hierarchical computer system

A computer system including a first repeater; a second repeater coupled to the first repeater; and a third repeater coupled to the first repeater. The second repeater is also coupled to a first client and a second client. The second repeater contains a distributed arbiter that predicts whether the first repeater will send a transaction to the second repeater.

Method and apparatus for efficiently broadcasting transactions between an address repeater and a client

A digital process monitor for measuring the performance of an integrated circuit has been developed. The digital process monitor includes: a ring oscillator that generates a series of clocked pulses, and a ripple counter that counts the clocked pulses. The count is measured for a prescribed period of time and the count corresponds to the performance of the integrated circuit.

Digital process monitor

A method for automatically arbitrating for mastership of a fiber channel loop in a host adapter circuit configured for coupling a host electronic device with the fiber channel loop. The host adapter circuit has a processor and a loop control circuit different from the processor. The loop control circuit is coupled to a memory of the host adapter circuit. The method includes sending out a host ARBITRATE primitive on the fiber channel loop. The method further includes employing the loop control circuit to monitor received ARBITRATE primitives received at the host adapter circuit from the fiber channel loop. There is also included ascertaining, using the loop control circuit, whether one of the received ARBITRATE primitives represents the host ARBITRATE primitive sent out previously. If the one of the received ARBITRATE primitives represents the host ARBITRATE primitive sent out previously, the method includes placing a target device coupled to the fiber channel loop in an OPENED state for receiving data from the host electronic device.

Fiber channel automatic arbitration and communication control

A method, in a host adapter circuit configured for coupling a host electronic device with one of a fiber channel loop and a point-to-point communication channel, for receiving data at the host adapter circuit from one of the fiber channel loop and the point-to-point communication channel. The method includes providing a selectable control signal configured for indicating whether the host adapter circuit is coupled to the fiber channel loop or the point-to-point communication channel. The method further includes providing a front-end receive circuit. The front-end receive circuit is configured for coupling with an input data port. The input data port represents one of the fiber channel loop and the point-to-point communication channel. The method also includes coupling the front-end receive circuit with the selectable control signal. Additionally, the method includes coupling an output of the front-end receive circuit with a decoder of the host adapter circuit, wherein the front-end receive circuit is configured to process, responsive to the selectable control signal, either fiber channel loop data from the fiber channel loop or point-to-point data from the point-to-point communication channel from the input data port to provide parallel data having a predefined size to the decoder circuit.

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San Jose, CA, United States of America

Tai Quan