Realtek Semiconductor Inc.

Tai-Jung Wu

Chun-Chieh Chan

Chia-Hao Chang

Ming-An Wu

Chien-Hsun Lu

Yu-Le Shen

The present disclosure discloses a signal relay apparatus having frequency locking mechanism that includes a receiving circuit, a frequency generation circuit, a frequency tracking circuit and a transmission circuit. The receiving circuit receives a receiving signal to retrieve data included therein according a corresponding receiving frequency signal. The frequency generation circuit receives a source clock signal and generates a target frequency signal according to a conversion parameter. The frequency tracking circuit calculates a frequency difference between the receiving frequency signal and the target frequency signal to adjust the conversion parameter accordingly. The transmission circuit generates a transmission signal that includes the data according to the target frequency signal.

Signal relay apparatus and method having frequency locking mechanism

The present disclosure discloses a video interface conversion device that includes a first and a second interface transmission circuit, a color conversion circuit and an image compression circuit. The first and the second interface transmission circuit are respectively electrically coupled to an image source and a display terminal. The second interface transmission circuit negotiates a maximum output bandwidth with the display terminal such that the first interface transmission circuit compares an input data bandwidth of a data signal received from the image source and the maximum output bandwidth. When the maximum output bandwidth is smaller than the input data bandwidth, an image compression and/or a color coding conversion is performed on the data signal, and the data signal having the processed input data bandwidth being smaller than or equal to the maximum output bandwidth is further transmitted by the second interface transmission circuit to the display terminal.

Video interface conversion device and method

The present invention discloses a signal relay apparatus having frequency calibration mechanism that includes a clock generation circuit, a frequency generation circuit, a clock measuring circuit, a frequency adjusting circuit and a transmission circuit. The clock generation circuit generates a source clock signal. The frequency generation circuit receives the source clock signal and generates a target frequency signal according to a conversion parameter. The clock measuring circuit measures a first frequency offset of a source frequency relative to a first predetermined frequency according to an external reference clock signal. The frequency adjusting circuit adjusts the conversion parameter according to the first frequency offset when the first frequency offset is not within a first predetermined range such that a second frequency offset of a target frequency relative to a second predetermined frequency is within a second predetermined range. The transmission circuit performs signal transmission according to the target frequency signal.

Signal relay apparatus and method having frequency calibration mechanism

An HDMI transmission device includes a packetizer circuit and a processor. A control method of controlling the HDMI transmission device includes performing a fixed rate link training, upon passing the fixed data rate link training, the processor transmitting an initial gap packet generation command to a controller of the packetizer circuit to output a selection signal to the packetizer circuit, so as to output an initial gap packet, when video data is not ready, continuously outputting the initial gap packet, when the video data is ready and a format change of the video data is detected or a signal abnormality unrelated to hot-plugging is detected, the processor transmitting a subsequent gap packet generation command to the controller to determine whether a block boundary is reached, and the controller switching the selection signal upon reaching the block boundary for the packetizer circuit to output the subsequent gap packet.

High definition multimedia interface transmission device and control method thereof

A video processing method and a video processor are provided. The video processing method can be utilized in a video processing system that includes a transmission terminal for generating an input video, the video processor, and a receiving terminal for receiving an output video. The method includes determining whether or not the input video is in at least one of an idle status, an unstable status and a terminated status; switching from outputting the output video to outputting a mute video when the input video is determined to be in at least one of the idle status, the unstable status and the terminated status; inserting a first general control packet for setting mute into one of a plurality of output frames of the mute video; and stopping outputting the mute video after the plurality of output frames of the mute video are outputted.

Video processing method and video processor

The present invention discloses a signal enhancement relay apparatus is provided. A display data channel stretching circuit includes a direct and an indirect channels. A snooper circuit is disposed at the direct channel. The indirect channel includes a master and a slave paths having a master and a slave transmission circuits disposed thereon. The direct channel is selected under a default passive mode such that a snooper link bridging handler circuit is enabled to monitor a display data transmission on the direct path through the snooper circuit, to perform a channel link bridging process corresponding to a data enhancement transmission channel accordingly. When the channel link bridging process under the passive mode fails, the indirect channel is selected under an active mode such that a intervening link bridging handler circuit t is enabled to access the display data transmission on the master and the slave paths respectively through the master and the slave transmission circuits, to perform the channel link bridging process respectively.

Growing community of inventors

Hsinchu, Taiwan

Tai-Jung Wu