Texas Instruments Corporation

Tai Huu Nguyen

Natarajan Kurian Seshan

Kenneth L Williams

Kevin A McGonagle

Jay Bryan Reimer

Harland Glenn Hopkins

Patrick J Smith

Yi Luo

Jason A Jones

Jason A T Jones

Jeffrey R Quay

Michael J Moody

Duy Q Nguyen

Jonathan G Bradley

Richard H Scales

Dan K Bui

Victor A Liu

H Glenn Hopkins

Irvinderpal S Ghai

Kenneth C Kelly

Jay B Reimer

Kevin A Mcgonagle

Jason AT Jones

Laurence RJr Simar

A processing system comprises a digital signal processor (DSP) device and a host system on which the DSP device is implemented. The DSP device comprises a shared program memory and a plurality of processor subsystems coupled to the shared program memory to concurrently execute program instructions stored in the shared program memory. The host system is capable of independently debugging each subsystem. During debugging, the host device inserts breakpoints into the shared program memory and tracks the debug breakpoints to determine which subsystems are associated with the breakpoints. When a subsystem executes a breakpoint associated with that subsystem, the subsystem halts until the host gathers necessary debug information from the subsystem. However, when a subsystem executes a breakpoint that is not associated with that subsystem, the host system causes the subsystem to execute the original program instructions and proceed as directed.

Debugger breakpoint management in a multicore DSP device having shared program memory

A digital signal processing system includes multiple processor subsystems, an external input/output port (XPORT), and an XPORT arbiter. The processor subsystems each include a processor core and a DMA controller. The XPORT arbiter arbitrates between the processor cores and between the DMA controllers, and further arbitrates between processor control or DMA control of the XPORT. Upon a request signal from a DMA controller, the XPORT arbiter asserts a hold signal to the processor cores. The processor cores respond by asserting a hold acknowledge signal. A processor core will delay the hold acknowledge signal until through with the XPORT. The arbiter, then asserts a grant signal to the DMA controller requesting access. The arbiter may assert a grant signal to a processor core requesting access. However, the processor core's access will be stalled as long as the hold signal is asserted.

External bus arbitration technique for multicore DSP device

A digital signal processing chip having a multiple processor cores with corresponding processor subsystems, a shared component, and a clock tree, is disclosed herein. A clock tree distributes clock signals to the processor cores and the shared component. The clock tree can be configured to disable one or more of the processor cores and the shared component by blocking the corresponding clock signal. This may advantageously conserve power. However, the clock tree is configured to preserve the clock signal to the shared component as long as at least one of the processor cores has not disabled the shared component. That is, to block the clock signal to the shared component, each of the processor cores must disable the shared component. The shared component may, for example, be a shared program memory or an arbiter for an external input/output port. The clock tree may include a register and a series of clock gates. Each of the clock gates blocks the clock signal when a gate signal is de-asserted. The gate signals are generated from enablement bits in the register. The clock signal for the shared component is gated by a clock gate that blocks the clock signal only if each of the processor cores have disabled their enablement bit for the shared component.

Unanimous voting for disabling of shared component clocking in a multicore DSP device

A multi-core digital signal processor is disclosed having a shared program memory with conditional write protection. In one embodiment, the digital signal processor includes a shared program memory, an emulation logic module, and multiple processor cores each coupled to the shared program memory by corresponding instruction buses. The emulation logic module preferably determines the operating modes of each of the processors, e.g., whether they are operating in a normal mode or an emulation mode. In the emulation mode, the emulation logic can alter the states of various processor hardware and the contents of various registers and memory. The instruction buses each include a read/write signal that, while their corresponding processor cores are in normal mode, is maintained in a read state. On the other hand, when the processor cores are in the emulation mode, the processor cores are allowed to determine the state of the instruction bus read/write signals. Each instruction bus read/write signal is preferably generated by a logic gate that prevents the processor core from affecting the read/write signal value in normal mode, but allows the processor core to determine the read/write signal value in emulation mode. In this manner, the logic gate prevents write operations to the shared program memory when the emulation logic de-asserts a signal indicative of emulation mode, and allows write operations to the shared program memory when the emulation logic asserts the signal indicative of emulation mode. The logic gate is preferably included in a bus interface module in each processor core.

Multicore DSP device having shared program memory with conditional write protection

A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment, each of the DMA controllers is coupled to each of the memory buses and is configured to control each of the memory buses. A memory bus multiplexer may be coupled between the subsystem memory bus and each of the DMA controllers, and an arbiter may be used to set the memory bus multiplexer so as to allow any one of the DMA controllers to control the memory bus. The memory bus may also be controlled by the host port interface via the memory bus multiplexer. A round-robin arbitration technique is used to provide each of the controllers and the host port interface fair access to the memory bus. This approach may advantageously provide increased flexibility in the use of DMA controllers to transfer data from place to place, with only a minimal increase in complexity.

Multicore DSP device having coupled subsystem memory buses for global DMA access

In order to sort signal group elements organized in blocks in a time-division multiplex protocol into frames of related elements, an address unit addresses the first element in each of the element blocks, then the second element in each element block, etc until all of the elements of all of the blocks have been addressed. In this manner, the related elements are sorted into frames of elements. The address unit performs this element sorting using a base address, an element index equal to the number of elements in a block, and a frame index equal to &lcub;the number of elements times (the number of frames minus one)&rcub; minus one as parameters.

Apparatus and method for a sorting mode in a direct memory access controller of a digital signal processor

As the digital signal processor has become more flexible, the direct memory access controller has assumed greater computational power to permit the core processing unit to perform its specialized processing without responding to signal transfer requests. Not only does the direct memory access controller control the exchange of signal groups between the memory unit and the core processing unit, but the direct memory access controller is also responsible for the transfer of signal groups within the digital signal processor that originate from the serial port, and the interface unit (the unit that implements the direct transfer of signal groups from the memory unit of one digital signal processor to a second signal processor). The direct memory access controller has programmable channels that permit the signal group source component to be coupled to the signal group destination component. The address unit of the direct memory access unit must be able to accommodate a plurality of addressing modes. An arbitration unit prevents conflict between the components. With respect to the host port interface unit, the exchange of the signal groups with the memory unit as performed by a direct transfer, the direct memory access controller preventing conflicting signal groups transfers.

Apparatus and method for the exchange of signal groups between a plurality of components in a digital signal processor having a direct memory access controller

A multi-core DSP device includes a shared program memory to eliminate redundancy and thereby reduce the size and power consumption of the DSP device. Because each of the program cores typically executes the same software program, memory requirements may be reduced by having multiple processor cores share only a single copy of the software. Accordingly, a program memory couples to each of the processor cores by a corresponding instruction bus. Preferably the program memory services two or more instruction requests in each clock cycle. Data is preferably stored in separate memory arrays local to the processor core subsystems and accessible by the processor cores via a dedicated data bus. In one specific implementation, the program memory includes a wrapper that can perform one memory access in the first half of each clock cycle and a second memory access in the second half of each clock cycle. A designated set of instruction buses is allowed to arbitrate for only the first access, and the remaining instruction buses are allowed to arbitrate for only the second access. In this manner, a reduction in on-board memory requirements and associated power consumption may be advantageously reduced.

Shared program memory for use in multicore DSP devices

A microprocessor is described which includes a multi-channel serial port (MCSP) . MCSP includes clock generation and frame sync generation circuitry , multi-channel selection circuitry , and companding circuitry . The clock generation and frame sync generation circuitry is configurable by means of a Serial Port Control Register SPCR, and Receive Control Register RCR, a Transmit Control Register XCR, a Sample Rate Generator Register SRGR, and Pin Control Register PCR. The multi-channel selection circuitry is configurable by means of a Multi-Channel Register MCR, a Receive Channel Enable Register RCER and a Transmit Channel Enable Register XCER. Companding circuitry performs optional expansion or compression of received or transmitted data using &mgr;-LAW or A-LAW, as selected by the Receive Control Register or the Transmit Control Register.

Multi-channel serial port with programmable features

A microprocessor 1 is described which includes a multi-channel serial port (MCSP) 120. MCSP 120 includes clock generation and frame sync generation circuitry 300, multi-channel selection circuitry 310, and companding circuitry 320. The clock generation and frame sync generation circuitry is configurable by means of a Serial Port Control Register SPCR, and Receive Control Register RCR, a Transmit Control Register XCR, a Sample Rate Generator Register SRGR, and Pin Control Register PCR. The multi-channel selection circuitry is configurable by means of a Multi-Channel Register MCR, a Receive Channel Enable Register RCER and a Transmit Channel Enable Register XCER. Companding circuitry 320 performs optional expansion or compression of received or transmitted data using .mu.-LAW or A-LAW, as selected by the Receive Control Register or the Transmit Control Register.

Growing community of inventors

Houston, TX, United States of America

Tai Huu Nguyen