International Business Machines Corporation

Tai Dinh Ngo

James Allan Kahle

Kurt Alan Feiste

Michael Putrino

Aubrey Deene Ogden

Philip George Shephard, Iii

Amy May Tuvell

Johm Victor Sell

A method and apparatus for testing a contents-addressable-memory type structure using a simultaneous write-thru mode in an array is provided. The circuit to be tested has combinational logic and an array, and the array has bit cells and a logic cells. Each logic cell is uniquely associated with a bit cell such that an output of a bit cell provides an input to a logic cell, and each set of logic cells for an address of the array provides an output data vector from the array. Each cone of logic in the combinational logic receives an output data vector from an associated address in the array as an input data vector, and each cone of logic in the combinational logic is independent from other cones of logic in the combinational logic. A test vector is input to a write port of the array, and a set of logic cell input values are also input into the array. A test write-thru mode signal simultaneously asserts all write wordline signals of the array associated with the write port in order to write the test vector to all addresses of the array. Test vectors can then be applied simultaneously to all the cones in the combinatorial logic instead of having to apply them to one array address at a time, thereby making it feasible to test this combinatorial logic using standard logic testing techniques. The non-CAM compare type array operations are then tested using ABIST techniques.

Method and apparatus for testing a contents-addressable-memory-type structure using a simultaneous write-thru mode

In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit. The store instruction is completed when all older instructions have completed and when all instructions in the instruction group have finished.

System and method for executing and completing store instructions

A single-precision floating-point register array for a floating-point execution unit that performs double-precision operations by emulation is provided. The register array comprises a plurality of single-precision floating-point registers and a storage device that stores one or more status bits in association with each of the plurality of registers; the status bits associated with each register indicate either that the associated data register contains single-precision or integer data, or that the data for the associated register is contained in an emulated register in memory that is mapped to the associated register. When a register is a source for an operation, the status bits associated with the register are checked and the required operand data for that register is read from the register or from an emulated register mapped to that register, as a function of the state of the status bits.

Single-precision, floating-point register array for floating-point units

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Austin, TX, United States of America

Tai Dinh Ngo