Taiwan Semiconductor Manufacturing Comp. Ltd.

Advanced Semiconductor Engineering, Inc.

Tai-Chun Huang

Tze-Liang Lee

Chi On Chui

Chih-Tang Peng

Chung-Ting Ko

Chih-Hsiang Yao

Ting-Gang Chen

Yung-Cheng Lu

Bo-Cyuan Lu

Yen-Chun Huang

Chieh-Ping Wang

Stefan Rusu

Hao-Ming Lien

Tien-I Bao

Bang-Tai Tang

Wan-Chen Hsieh

Pei-Ren Jeng

Li-Ting Wang

Bor Chiuan Hsieh

Chia-Hui Lin

Chin-Chiu Hsia

Kuan-Shou Chi

Chin-Hsiang Lin

Ming-Hua Yu

Shu-Yuan Ku

Jr-Hung Li

Chia-Wei Chang

Teng-Chun Tsai

Ryan Chia-Jen Chen

Kuang-Yuan Hsu

Ming-Chang Wen

Wen-Kai Wan

Hong-Hsien Ke

Syun-Ming Jang Jang

Chewn-Pu Jou

Chao-Cheng Chen

Fu-Kai Yang

Huan-Just Lin

Lan-Chou Cho

Su Tao

Cheng-Tung Lin

De-Fang Chen

Yi-Hung Lin

Chien-Hsun Wang

Min-Hwa Chi

Chunyao Wang

Ming-Jie Huang

Sung-En Lin

Shih-Wen Huang

Po-Hsien Cheng

Ya-Lan Chang

Yi-Ting Fu

Wen-Ju Chen

Jr-Yu Chen

Wen-ju Chen

Yee-Chia Yeo

Huicheng Chang

Mong-Song Liang

Ming-Ching Chang

Yu-Chang Lin

Wen-Yen Chen

Tsu-Hsiu Perng

Jian-Shiou Huang

Wei-Che Hsieh

Chien Chung Huang

Kai Hung Cheng

Shiang-Rung Tsai

Wen-Cheng Wu

Yi-Chao Wang

Wan-Hsien Lin

Chien-Kuo Huang

Brian Wang

Chih-Fang Liu

Ching-Hua Hsieh

Chun-Hung Lin

Cheng-Ming Lin

Chia-Ying Lee

Ming-Ta Lei

Chun-Yi Lee

Han-Yu Lin

Joy Cheng

Ting-Ting Chen

Yu-Chung Su

Wei-Yen Woon

Tsai-Fu Hsiao

Kuo-Pin Yang

Shin-Hua Chao

Szuya Liao

Shih-Kuang Chen

Chih-Cherng Jeng

Ling-Fu Nieh

Ming-Fa Wu

Pin-Chuan Su

Cheng-tse Tang

Chang-Shen Lu

Ming-Shuoh Liang

Bi-Trong Chen

Szu-Hua Chen

Chun-Ming Lung

Chun-Yao Wang

A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.

Trench filling through reflowing filling material

The present disclosure provides a calibration system for wavelength-division multiplexing (WDM), a WDM system, and a calibrating method for WDM. The calibration system includes heating devices, an optical sensor, and an electrical device. When the optical sensor receives no beam with energy exceeding a threshold value from a first channel, the optical sensor transmits a first signal to the electrical device. In response to the first signal, the electrical device is configured to control the one or more of the heating devices to heat one or more of channels. When the optical sensor receives a beam having energy exceeding the threshold value from the first channel, the optical sensor transmits a second signal to the electrical device. In response to the second signal, the electrical device is configured to control the one or more of the heating devices to maintain the temperature of the one or more of the channels.

Calibration system for wavelength-division multiplexing, wavelength-division multiplexing system, and calibrating method for wavelength-division multiplexing

A method for forming a semiconductor structure is provided. The method includes forming a first active region and a second active region, etching the first active region and the second active region to form a first recess and a second recess, respectively, forming the first dielectric layer over the first active region and the second active region, forming a first fill layer over the first dielectric layer to overfill the first recess and the second recess, forming a first dielectric mask over the first fill layer, etching first portions of the first dielectric mask and the first fill layer over the first active region, removing a first portion of the first dielectric layer over the first active region, and forming a first source/drain feature on the first active region.

Method for forming semiconductor structure

A photonic vertical grating filter is disclosed. The filter comprises a first waveguide, a second waveguide, and a plurality of Bragg gratings. The Bragg gratings are formed in a dielectric layer between the first waveguide and the second waveguide, and are located in a vertical overlap region between the first waveguide and the second waveguide. Each Bragg grating has a different grating period. The vertical filter uses less surface area and provides improved filtering capabilities.

Vertical grating filters for photonics

A semiconductor device having a low-k isolation structure and a method for forming the same are provided. The semiconductor device includes channel structures, laterally extending on a substrate; gate structures, intersecting and covering the channel structures; and a channel isolation structure, laterally penetrating through at least one of the channel structures, and extending between separate sections of one of the gate structures along an extending direction of the one of the gate structures. A low-k dielectric material in the channel isolation structure comprises boron nitride.

Semiconductor device having isolation structure formed of low-k dielectric material and method for forming the same

A method includes forming a first gate stack over a first semiconductor region, depositing a spacer layer on the first gate stack, and depositing a dummy spacer layer on the spacer layer. The dummy spacer layer includes a metal-containing material. An anisotropic etching process is performed on the dummy spacer layer and the spacer layer to form a gate spacer and a dummy sidewall spacer, respectively. The first semiconductor region is etched to form a recess extending into the first semiconductor region. The first semiconductor region is etched using the first gate stack, the gate spacer, and the dummy sidewall spacer as an etching mask. The method further includes epitaxially growing a source/drain region in the recess, and removing the dummy sidewall spacer after the source/drain region is grown.

Method of forming thin dummy sidewall spacers for transistors with reduced pitches

A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

Semiconductor device, FinFET device and methods of forming the same

A semiconductor device a method of forming the same are provided. The semiconductor device includes a substrate, a first isolation structure and a second isolation structure over the substrate, a semiconductor fin over the substrate and between the first isolation structure and the second isolation structure, and a third isolation structure extending through the semiconductor fin and between the first isolation structure and the second isolation structure. A top surface of the semiconductor fin is above a top surface of the first isolation structure and a top surface of the second isolation structure. The third isolation structure includes a first dielectric material and a second dielectric material over the first dielectric material. An interface between the first dielectric material and the second dielectric material is below the top surface of the first isolation structure and the top surface of the second isolation structure.

FinFET device and method of forming same

A gate stack can be etched to form a trench extending through the gate stack, the trench removing a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion. A dielectric material is deposited in the trench to form a dielectric region, the dielectric region having an air gap in the dielectric material. The air gap may extend upward from beneath the gate stack to an area interposed between the end of the first gate stack portion and the end of the second gate stack portion. Contacts to the first gate stack portion and contacts to the second gate stack portion may be formed which are electrically isolated from each other by the dielectric material and air gap formed therein.

Cut metal gate refill with void

A method of forming an optical device is provided that can include forming a backside reflector layer, and forming a cladding layer on the backside reflector layer. The method can further include forming a grating layer on the cladding layer, and forming a receiving reflector layer on the cladding layer. The receiving reflector layer can include an opening for receiving optical signal to at least the grating layer.

Reflectors applied to photonics platforms

A method includes forming an etching mask, which includes forming a bottom anti-reflective coating over a target layer, forming an inorganic middle layer over the bottom anti-reflective coating, and forming a patterned photo resist over the inorganic middle layer. The patterns of the patterned photo resist are transferred into the inorganic middle layer and the bottom anti-reflective coating to form a patterned inorganic middle layer and a patterned bottom anti-reflective coating, respectively. The patterned inorganic middle layer is then removed. The target layer is etched using the patterned bottom anti-reflective coating to define a pattern in the target layer.

Multi-layer photo etching mask including organic and inorganic materials

A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.

Semiconductor device with isolation structure

Multi-layer photoresists, methods of forming the same, and methods of patterning a target layer using the same are disclosed. In an embodiment, a method includes depositing a reflective film stack over a target layer, the reflective film stack including alternating layers of a first material and a second material, the first material having a higher refractive index than the second material; depositing a photosensitive layer over the reflective film stack; patterning the photosensitive layer to form a first opening exposing the reflective film stack, patterning the photosensitive layer including exposing the photosensitive layer to a patterned energy source, the reflective film stack reflecting at least a portion of the patterned energy source to a backside of the photosensitive layer; patterning the reflective film stack through the first opening to form a second opening exposing the target layer; and patterning the target layer through the second opening.

Photoresist and method

A vertical grating coupler is disclosed. The grating coupler includes a first waveguide having a first grating, a second waveguide having a second grating, and a dielectric layer positioned between the first waveguide and the second waveguide. The first grating includes a plurality of first grating ridges separated by a plurality first grating gaps, and the second grating includes a plurality of second grating ridges separated by a plurality second grating gaps. The first grating, the second grating, and the dielectric layer are located in a vertical overlap region between the first waveguide and the second waveguide. The first grating and the second grating have different grating periods, and each of the plurality of first grating gaps and second grating gaps are filled with the dielectric layer.

Vertical grating coupler

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes an isolation structure formed over a semiconductor substrate. A first fin structure and a second fin structure extend from the semiconductor substrate and protrude above the isolation structure. A first gate structure is formed across the first fin structure and a second gate structure is formed across the second fin structure. A gate isolation structure is formed between the first fin structure and the second fin structure and separates the first gate structure from the second gate structure. The gate isolation structure includes a bowl-shaped insulating layer that has a first convex sidewall surface adjacent to the first gate structure and a second convex sidewall surface adjacent to the second gate structure.

FinFET with bowl-shaped gate isolation and method

Growing community of inventors

Hsinchu, Taiwan

Tai-Chun Huang