Institute of Microelectronics

Agency for Science, Technology and Research

Texas Instruments Corporation

Tai Chong Chai

Thiam Beng Lim

Kishore Kumar Chakravorty

Daniel Yap

Sarvotham M Bhandarkar

Jian Hua Wu

James Tan

Yong Chua Teo

Eric Neo

Vaidyanathan Kripesh

Raymundo M Camenforte

Mahadevan Krishna Iyer

David Ho

Mihai Dragos Rotaru

Xiaowu Zhang

Wai Kwan Wong

Surya Bhattacharya

Boon Q Seow

Tadashi Saitoh

Xian Tong Chen

Vempati Srinivasa Rao

Cheng Kuo Cheng

Ray Camenforte

Kripesh Vaidyanathan

Cheryl Sharmani Selvanayagam

Karta W Tjandra

Alastair David Trigg

Various embodiments may provide an electrical connection structure. The electrical connection structure may include a first substrate having a first surface defining a cavity, and an inner wall defining a via extending from the cavity. The electrical connection structure may also include an interconnect structure provided in the via so that at least a portion of the interconnect structure protrudes into the cavity. The electrical connection structure may further include a second substrate having a second surface facing the first surface. The electrical connection structure may additionally include a connection element on the second surface. At least a portion of the connection element may be received in the cavity so that the connection element is in electrical connection with the interconnect structure.

Electrical connection structure, semiconductor package and method of forming the same

A bonding stress testing arrangement and a method of determining stress are provided. The bonding stress testing arrangement includes at least one bond pad; a sensor assembly comprising any one of a first sensor arrangement, a second sensor arrangement and a combination of the first sensor arrangement and the second sensor arrangement; wherein the first sensor arrangement is adapted to measure an average stress on a portion of a bonding area under the at least one bond pad, and the second sensor arrangement is adapted to determine stress distribution over a portion or an entire of the bonding area under the at least one bond pad.

Bonding stress testing arrangement and method of determining stress

A wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed. The wafer level package comprises at least one first, second and third separation layer having at least one first and second conductive layer formed in-between the separation layers. The at least one first conductive layer is formed on the at least one first separation layer and is coupled to the bondpads. The at least one second conductive layer is formed on the at last one second separation layer wherein the at least one second conductive layer is electrically coupled to the at least one first conductive layer. The at least one third separation layer allows solder to be attached to the at least one second conductive layer for electrically coupling the solder to the bondpads. A chip ground plane is laid in the integrated circuit chip for providing a ground to the at least one first conductive layer and the solder.

Wafer level packages and methods of fabrication

A lead-frame for connecting and supporting an integrated circuit having an apertured frame with dimensions smaller than the corresponding dimensions of the chip so that chip-pad shoulder can be eliminated and the chip attach fillet is made remote from the chip corner.

Lead frame for an integrated circuit chip

A lead-frame for connecting and supporting an integrated circuit chip with a chip accommodating zone with inwardly extending ears for supporting the chip including minimum shoulder area, and having open crack and delamination stopping regions.

Lead frame for an integrated circuit chip (integrated circuit peripheral support)

A dispenser contains a chamber enclosed by an upper wall and a lower wall, both walls are oriented parallel to each other. The upper wall has a vertically bored inlet port and the lower wall has a plurality of vertically bored outlet ports for providing access to the chamber. The outlet ports are geometrically arranged in an array pattern characterized by equidistantly spaced rows and columns of bores. There is a plurality of baffle plates interposed between the upper wall and the lower wall. The baffle plates, which are spatially separated from each other, are oriented parallel to and spatially separated from the upper and lower walls. The baffle plates have a plurality of vertically bored holes for providing access between the inlet port and the outlet ports, whereby the dispenser is effective in providing homogeneous flow of fluid through the outlet ports.

Apparatus for dispensing fluid in an array pattern

An insulated lead frame for a semiconductor packaged device and a method of manufacturing both the insulated lead frame and the semiconductor packaged device are disclosed. The insulated lead frame has a first plurality of lead fingers and a second plurality of lead fingers. It also has the face of a power supply bus lying between the pluralities of lead fingers. An insulator covers the face of the power supply bus. An example of an insulator is a cured liquid polyimide. In a semiconductor packaged device using a lead on chip lead frame, such as a dynamic random access memory, DRAM, wire bonding that connects the power supply busses of the lead frame may first occur and the liquid insulator may afterwards be applied to the power supply busses. Alternatively, by knowing where the wire bonds will bond to the power supply busses, the liquid insulator may be applied to the power supply busses before wire bonding occurs. The bonding spots on the power supply busses are not covered with the liquid insulator. Both methods serve to reduce the possibility of shorting between the power supply busses and the crossing wire bonds that connect the lead fingers of the lead frame to the bonding pads of the integrated circuit.

Method of manufacturing insulated lead frame for integrated circuits

Growing community of inventors

Singapore, Singapore

Tai Chong Chai