National Taiwan University

Mediatek Corporation

Realtek Semiconductor Inc.

Digwise Technology Corporation, Ltd

Tai-Cheng Lee

Chih-Lung Chen

Shih-Hsiung Huang

Yu-Chang Chen

Shih-Hao Chen

Jie-Fan Lai

Wen-Pin Hsieh

Sheng-Yen Shih

Yen-Chuan Huang

Chin-Yu Lin

Li-Han Hung

Tzu-Hao Hung

Chiou-Bang Chen

Chien-Heng Wong

Cheng-Hsiao Lin

Yao-Ming Lu

Yan-Hui Wu

Yen-Hsin Wei

Heng-Jui Liu

A continuous-time delta-sigma modulator (CT-DSM) includes a loop filter, a pipelined successive-approximation register analog-to-digital converter (SAR ADC), a feedback circuit, an excess loop delay (ELD) compensation circuit, and a logic circuit. The loop filter generates a first intermediate signal according to an input signal, a feedback signal, and a compensation signal. The pipelined SAR ADC generates a first digital code, a second digital code, a first quantization error signal, and a second quantization error signal according to the first intermediate signal. The feedback circuit generates the feedback signal according to the first digital code, the first quantization error signal, and the second quantization error signal. The ELD compensation circuit generates the compensation signal according to at least one output signal of the feedback circuit. The logic circuit generates an output digital code according to the first digital code and the second digital code.

Continuous-time delta-sigma modulator

A clock and data recovery circuit includes a first sampling phase detector and filter circuitry, a frequency detector circuit, a current source circuit, a band controller circuit, and a voltage controlled oscillator. The first sampling phase detector and filter circuitry generates a first voltage according to a pair of data and a first set of clock signals. The frequency detector circuit generates an up control signal and a down control signal according to the pair of data and the first set of clock signals. The current source circuit generates the first voltage according to the up control signal and the down control signal. The band controller circuit generates a band control signal according to the first voltage. The voltage controlled oscillator adjusts the first set of clock signals according to the band control signal and the first voltage.

Clock and data recovery circuit

An analog-to-digital converter (ADC) device includes an ADC circuitry and a digital slope ADC circuitry. The ADC circuitry is configured to generate first bits and a first voltage according to an input signal. The digital slope ADC circuitry is configured to generate a second voltage at a node according to the first voltage and to gradually adjust the second voltage to generate second bits. After the second bits are generated, the digital slope ADC circuitry is further configured to perform a noise shaping function according to a first residual signal of the node.

Analog to digital converter device and noise shaping digital slope analog to digital converter circuitry

An analog-to-digital converting system includes at least one first main analog-to-digital converting unit, at least one second main analog-to-digital converting unit, at least one auxiliary analog-to-digital converting unit, and a calibration unit. Each first main analog-to-digital converting unit is located on a first channel. The first channel includes sample period. Each first main analog-to-digital converting unit receives a first sampling value. Each first sampling value includes a first sample clock. An analog-to-digital converting method calibrates timing-skew of the analog-to-digital converters by delaying a time difference on the sampling value.

Analog-to-digital converting system and converting method

A spread spectrum transmission circuit includes a phase locked loop composed of a filter. The phase locked loop generates a series of incremental control signals and decreasing control signals based on the frequency difference and phase difference between a reference clock signal and a feedback signal. The circuit further has a frequency locked loop an amplitude locked loop, a digital-analog converter, an injection current source, an extraction current source, a multiplexer is connected to the locked phase loop and a rail-to-rail digital signal generator having an input connected to the multiplexer and an output connected to inputs of the locked frequency loop and the locked amplitude loop.

Circuit for spread spectrum transmission and method thereof

A pipelined analog-to-digital converter with less power consumption is provided. In one embodiment, the pipelined analog-to-digital converter comprises a first stage, a second stage, and a third stage. The first stage receives a first stage input signal to derive a first stage output signal and a first residue. The second stage receives a second stage input signal to derive a second stage output signal and a second residue, wherein the second stage input signal corresponds to the first residue. The third stage receives a third stage input signal to derive a third stage output signal and a third residue, wherein the third stage input signal corresponds to the second residue. The first, second and third stages share an operational amplifier by utilizing at least three phases to control the operational amplifier.

Pipelined analog-to-digital converter and method for converting analog signal to digital signal

The digital-to-analog converter in accordance with the present invention comprises an R-2R transistor-only ladder converter and a digital controller. The controller connects to the R-2R transistor-only ladder converter and comprises at least one regulating transistor and at least one shifting transistor. The at least one regulating transistor has an aspect ratio of k(W/L). The at least one shifting transistor has an aspect ratio of k(W/L). Setting the aspect ratios k(W/L) and k(W/L) of the shifting and regulating transistors adjusts a linear output current waveform to a non-linear waveform. The method to output a non-linear current comprises acts of determining an optimum non-linear output current, dividing a linear output current into multiple sections, determining slopes of the waveform of the output current, adding a controller corresponding to an R-2R transistor-only ladder converter, setting aspect ratios k(W/L) of regulating transistors and setting an aspect ratios k(W/L) of shifting transistors.

Digital-to-analog converter (DAC) and an associated method

A method for achieving high-speed analog-to-digital conversion without degrading accuracy includes: receiving digital outputs of a plurality of pipelined analog-to-digital converters (ADCs) that perform analog-to-digital conversion on a same analog signal; and performing digital calculations on the digital outputs to generate a calibrated digital output. An apparatus for achieving high-speed analog-to-digital conversion without degrading accuracy is further provided. The apparatus includes: a digital module arranged to receive digital outputs of a plurality of pipelined ADCs that perform analog-to-digital conversion on a same analog signal. In addition, the digital module includes a plurality of digital calculation paths respectively corresponding to the pipelined ADCs, wherein each digital calculation path corresponding to an associate pipelined ADC of the pipelined ADCs is electrically connected to the associate pipelined ADC. The digital module performs digital calculations on the digital outputs to generate a calibrated digital output.

Growing community of inventors

Taipei, Taiwan

Tai-Cheng Lee