Advanced Micro Devices Corporation

Tai C Shyu

Lee-Lean Shu

Patrick T Chuang

Chao-Ven Kao

A system for preventing forward biasing of the bit line junctions formed between the N-well and bit lines of a CMOS memory. The system includes a gating system for maintaining the bit line voltage at V.sub.CC /2 whenever the well voltage is less than V.sub.CC. A well regulator and well pump maintain the well voltage at a selected multiple of V.sub.CC.

CMOS N-well bias generator and gating system

A low power, low output impedance, CMOS voltage reference with high source/sink current driving capability. A CMOS current mirror preamplifier includes matched transistor pairs having their W/L ratios scaled to reduce the level of current to the subthreshold region. A CMOS source follower output stage also has its transistors biased in the subthreshold region. Circuitry for protecting the preamplifier from the effects of supply voltage and output voltage bumps is also disclosed.

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San Jose, CA, United States of America

Tai C Shyu