Macronix International Co., Ltd.

Tahone Yang

Kuang-Chao Chen

Tuung Luoh

Chin-Ta Su

Ling-Wu Yang

Chao-Lung Lo

Tien-Chu Yang

ChungTe Hsuan

Chien Hung Chen

Ricky Huang

Ming Da Cheng

Sheng Hui Hsieh

Methods for fabricating conductive metal lines of a semiconductor device are described herein. In one embodiment, such a method may comprise depositing a conductive material over a substrate, and depositing a first barrier layer on the conductive layer. Such a method may also comprise patterning a mask on the first barrier layer, the pattern comprising a layout of the conductive lines. Such an exemplary method may also comprise etching the conductive material and the first barrier layer using the patterned mask to form the conductive lines. In addition, a low temperature post-flow may be performed on the structure. The method may also include depositing a dielectric material over and between the patterned conductive lines.

Method for fabricating conductive lines of a semiconductor device

A system and method for modifying an integrated circuit (IC) layout includes performing a correction process, such as an optical proximity correction (OPC) process, only on regions within designated blocks that are defined around respective modified structures. An IC layout can be compared to a modified version of the IC layout to detect modified structures. One or more large blocks can then be defined around respective modified structures. A correction process can then be performed on only the one or more large blocks. Small blocks within respective large blocks can then be extracted from the modified IC layout and merged with the original IC layout to generate a final modified and corrected IC layout.

System and method for optical proximity correction of a modified integrated circuit layout

Techniques for forming metal silicide contact pads on semiconductor devices are disclosed, and in one exemplary embodiment, a method may comprise depositing a metal layer on and between a plurality of raised silicon-based features formed on a semiconductor substrate, the metal layer comprising metal capable of reacting with external silicon-based portions of the features to form a metal silicide. In addition, such a method may also include depositing a cap layer on the metal layer deposited on and between the plurality of raised silicon-based features, wherein a thickness of the cap layer on the metal layer between the raised features is greater than or equal to a thickness of the cap layer on the metal layer on the raised features. Furthermore, such a method may also include annealing the structure to cause portions of the metal layer to react with portions of the external silicon-based portions of the features to form metal silicide pads on and between the raised features.

Metal silicide formation

The method of forming a wordline is provided in the present invention. The proposed method includes steps of: (a) providing a plurality of SASTIs with a plurality of first POLY cells deposited thereon; and (b) depositing a first fill-in material having a relatively high etching rate oxide-like material in the plurality of SASTIs and on each side wall of the plurality of first POLY cells.

Methodology for wordline short reduction

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Miaoli, Taiwan

Tahone Yang