Apple Inc.

Tahoma Madrone Toelkes

Michael J Smith

Nir Jacob Wakrat

Dallas Blake De Atley

Gordon J Freedman

Paul William Chinn

David Rahardja

Thomas Brogan Duffy, Jr

Daniel Jeffrey Post

Kenneth Louis Herman

Vadim Khmelnitsky

Anthony Fai

Douglas C Lee

Diarmuid P Ross

Matthew John Byom

Barry J Corlett

Hsiao Thio

Jerrold Von Hauck

Michael Brouwer

Jason D Gosnell

Douglas Lee

Disclosed herein are systems, methods, and non-transitory computer-readable storage media for erasing user data stored in a file system. The method includes destroying all key bags containing encryption keys on a device having a file system encrypted on a per file and per class basis, erasing and rebuilding at least part of the file system associated with user data, and creating a new default key bag containing encryption keys. Also disclosed herein is a method of erasing user data stored in a remote file system encrypted on a per file and per class basis. The method includes transmitting obliteration instructions to a remote device, which cause the remote device to destroy all key bags containing encryption keys on the remote device, erase and rebuild at least part of the file system associated with user data, and create on the remote device a new default key bag containing encryption keys.

System and method for wiping encrypted data on a device having file-level content protection

Systems and methods are provided for dynamically allocating a number of bits per cell to memory locations of a non-volatile memory ('NVM') device. In some embodiments, a host may determine whether to store data in the NVM device using SLC programming or MLC programming operations. The host may allocate an erased block as an SLC block or MLC block based on this determination regardless of whether the erased block was previously used as an SLC block, MLC block, or both. In some embodiments, to dynamically allocate a memory location as SLC or MLC, the host may provide an address vector to the NVM package, where the address vector may specify the memory location and the number of bits per cell to use for that memory location.

Dynamically allocating number of bits per cell for memory locations of a non-volatile memory

Systems, apparatuses, and methods are provided for whitening and managing data for storage in non-volatile memories, such as Flash memory. In some embodiments, an electronic device such as media player is provided, which may include a system-on-a-chip (SoC) and a non-volatile memory. The SoC may include SoC control circuitry and a memory interface that acts as an interface between the SoC control circuitry and the non-volatile memory. The SoC can also include an encryption module, such as a block cipher based on the Advanced Encryption Standard (AES). The memory interface can direct the encryption module to whiten all types of data prior to storage in the non-volatile memory, including sensitive data, non-sensitive data, and memory management data. This can, for example, prevent or reduce program-disturb problems or other read/write/erase reliability issues.

Data whitening for writing and reading data to and from a non-volatile memory

The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.

Architecture for address mapping of managed non-volatile memory

Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.

Multipage preparation commands for non-volatile memory systems

Systems and methods are provided for using a NAND-type non-volatile memory ('NVM'), such as NAND flash memory, to store NV pre-boot information for a bootloader (e.g., a second state bootloader) or an operating system. The NV pre-boot information can include, for example, environment variables storing the configuration or state of an electronic device. In some embodiments, an electronic device including the NAND-type NVM may allocate a portion of the super blocks in the NAND-type NVM to storing the NV pre-boot information. The electronic device may store a redundant copy of the NV pre-boot information into the allocated portion of each IC die of the NAND-type NVM.

Device bootup from a NAND-type non-volatile memory

Securely installing and booting software of a device to run OS authorized according to a ticket that is validated by a nonce generated by application processor (AP) in booted OS stage prior to entering a restore mode is described. AP in booted OS stage generates a pre-flight nonce that is stored in a trusted location (effaceable storage). AP in booted OS stage performs one-way hash of pre-flight nonce and sends the hashed pre-flight nonce to ticket authorization server. AP enters restore mode. AP in first stage bootloader receives a ticket from the ticket authorization server including a signed copy of the hashed pre-flight nonce. AP in first stage bootloader validates the signed ticket by comparing one-way hash of the pre-flight nonce stored in the trusted location and the hashed nonce in the signed ticket. Pre-flight nonce expires after timeout period and upon reboot of AP. Other embodiments are also described.

Ticket-based personalization

Techniques for booting a computing device with a flash memory without knowledge of parametric information of the flash memory are described herein. In one embodiment of the invention, the computing device receives input requesting the computing device to begin operation and executes a set of one or more instructions stored in a non-volatile memory. The execution of the set of instructions configures a first read routine for accessing the flash memory based on a common denominator format of candidate flash memories, and the first read routine is not configured based on information located in a flash memory identification table. The computing device reads a bootstrapping code image based on the first read routine into a volatile memory and executes that first bootstrapping code image. Other methods and apparatuses are also described.

Method and apparatus for booting from a flash memory

In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. In an embodiment, a macro memory may store command sequences to be performed in response to a macro command in the command queue. In an embodiment, an operand queue may store operand data for use by the commands.

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San Jose, CA, United States of America

Tahoma Madrone Toelkes