Hrl Laboratories, LLC

Raytheon Company

Tahir Hussain

Miroslav Micovic

James Chingwei Li

Paul B Hashimoto

David H Chow

Peter David Brewer

Dana C Wheeler

Rajesh D Rajavel

Hasan Sharifi

Pamela R Patterson

Kyung-Ah Son

Wonill Ha

Marko Sokolich

Ara K Kurdoghlian

Yakov Royter

Aurelio Lopez

Gary Peng

Jeong-sun Moon

Keisuke Shinohara

Zhiwei A Xu

Jongchan Kang

Wah S Wong

Shawn D Burnham

Brian N Limketkai

Mary C Montes

Partia Naghibi-Mahmoudabadi

Mike Antcliffe

James H Schaffner

Christopher Stephen Roper

Hyok Jae Song

Joseph S Colburn

Biqin Huang

Erik S Daniel

Peter W Deelman

Harris P Moyer

Steven S Bui

Janna Ruth Duvall

Partia Naghibi Mahmoudabadi

Eason F Wang

A method and apparatus for laterally urging two semiconductor chips, dies or wafers into an improved state of registration with each other, the method and apparatus employing microstructures comprising: a first microstructure disposed on a first major surface of a first one of said two semiconductor chips, dies or wafers, wherein the first microstructure includes a sidewall which is tapered thereby disposing it at an acute angle compared to a perpendicular of said first major surface, and a second microstructure disposed on a first surface of a second one of said two semiconductor chips, dies or wafers, wherein the shape of the second microstructure is complementary to, and mates with or contacts, in use, the first microstructure, the second microstructure including a surface which contacts said sidewall when the first and second microstructures are mated or being mated, the sidewall of the first microstructure and the surface of the second microstructure imparting a lateral force for urging the two semiconductor chips, dies or wafers into said improved state of registration.

Integrated mechanical aids for high accuracy alignable-electrical contacts

A method for bonding two confronting electronic devices together wherein the two electronic devices are initially temporarily coupled together using a room temperature process with a plurality of knife-edge microstructures on at least a first one of the electronic devices engaging portions of the a second one of the electronic devices. The room temperature process involves applying a relatively low compressive force or pressure between the two electronic devices compared to the forces or pressures used in convention flip-chip bonding. The first one of the electronic devices and the second one of the electronic devices also have traditional contact pads that are spaced from each other by a standoff distance when the devices are initially coupled together using the room temperature process. This allows for inspection of the two electronic devices while they are initially temporarily coupled together. In need be, the two can be separated at this stage for re-work After passing inspection, a relatively higher compressive force or pressure is applied between the two electronic devices to cause the standoff distance to decrease to zero and for the contact pads confronting each other on the confronting two electronic devices to weld thereby permanently bonding the two electronic devices together.

Temporary bonding structures for die-to-die and wafer-to-wafer bonding

A semiconductor power handling device, includes a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode by a nano-vacuum gap. An array of semiconductor power handling devices, each comprising a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode pillar by a nano-vacuum gap. The semiconductor power handling devices can be arranged as rows and columns and can be interconnected to meet the requirements of various applications. The array of power handling devices can be fabricated on a single substrate.

Nano vacuum gap device with a gate-all-around cathode

A neuroelectric sensor and stimulator system includes a first antenna, a reader coupled to the first antenna for transmitting stimulation controls and power to a second antenna, and for receiving sensor data transmitted from the second antenna via the first antenna, and at least one neuroelectric sensor stimulator array including the second antenna, a rectifier coupled to the second antenna for extracting power transmitted from the first antenna, a controller coupled to the second antenna for decoding controls transmitted from the first antenna to the second antenna for the neuroelectric sensor stimulator array, a plurality of sensors, a multiplexer coupled to the controller and to the plurality of sensors for selecting a single sensor, and a plurality of stimulators coupled to the controller for stimulating neurons, wherein the rectifier, the controller, the plurality of sensors, the multiplexer, and the plurality of stimulators include graphene.

Scalable high-density wireless neuroelectric sensor and stimulator array

A compound semiconductor integrated circuit comprising a first substrate; a first electronic component formed on top of said first substrate; a layer of a first dielectric material formed on top of said first substrate and including said first electronic component, said layer of a first dielectric material comprising a recess exposing a first region of said first substrate; and a layer of a second dielectric material attached to said first substrate on top of said first region of said first substrate after manufacturing of said layer of a second dielectric material, said layer of a second material comprising a second electronic component.

Monolithic integration of GaN and InP components

The disclosed antenna structures and electronic microsystems are capable of physically disappearing in a controlled, triggerable manner. Some variations provide an on-chip transient antenna comprising a semiconductor substrate containing ion-implanted hydrogen atoms and a conductor network comprising metals bridged by low-melting-temperature metals. Some variations provide an off-chip transient antenna comprising a flexible substrate containing a polymer, nanoporous silicon particles, and an oxidant for silicon, and a conductor network comprising metals bridged by low-melting-temperature metals. Other variations provide a method of introducing physical transience to a semiconductor integrated circuit, comprising thinning a substrate from the back side, implanting hydrogen ions into the thinned substrate to introduce latent structural flaws, depositing a semiconductor integrated circuit or sensor chip, and providing a controllable heating source capable of activating the latent structural flaws. These novel approaches are compatible with existing integrated circuits processing, preserve antenna performance, and use foundry-compatible techniques.

Transient antennas and transient electronics

A method for fabricating a digital memristor crossbar array includes applying a protective layer on at least a portion of a memristive layer. A method for fabricating an analog memristor crossbar array includes providing a self-aligning first electrode layer. An analog memristor includes a memristive layer bar arranged to self-align said second electrode on said memristive layer along its length.

Memristor devices and fabrication

A field effect transistor (FET) having a source, a drain and a gate includes a first connection electrically connected to the gate near a first end of the gate, a second connection electrically connected to the gate near the first end of the gate, a third connection electrically connected to the gate near a second end of the gate, and a fourth connection electrically connected to the gate near the second end of the gate. By performing gate resistance measurements at different ambient temperatures, a thermal coefficient of gate resistance can be derived and then used to monitor the gate temperature, which is representative of the channel temperature.

Test structure to monitor the in-situ channel temperature of field effect transistors

A method of fabricating a normally 'off' GaN heterostructure field effect transistor having a source and a drain including depositing a passivation layer patterned to cover a channel region between a source and a drain, forming a first opening in the passivation layer, the first opening for defining a gate area in the channel region and the first opening having a first length dimension along a direction of current flow between the source and the drain, and implanting ions in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension.

Enhancement mode normally-off gallium nitride heterostructure field effect transistor

A method of three dimensional heterogeneous integration including forming HBT devices on a first substrate, each HBT device having a collector, removing the first substrate, forming first bonding pads on each collector of the heterojunction bipolar transistor devices, forming high electron mobility transistor (HEMT) devices on a first side of a growth substrate, wherein the growth substrate comprises a thermally conductive substrate, such as SiC or diamond, forming second bonding pads on the first side of the growth substrate, aligning and bonding the first bonding pads to the second bonding pads, forming CMOS devices on a Si substrate, bonding the CMOS devices on the Si substrate to a second side of the growth substrate, and forming selectively interconnects between the HBT devices, the HEMT devices, and the CMOS devices by forming vias and first and second level metal interconnects.

Thermal management for heterogeneously integrated technology

A heterojunction bipolar transistor (HBT) having an emitter, a base, and a collector, the base including a first semiconductor layer coupled to the collector, the first semiconductor layer having a first bandgap between a first conduction band and a first valence band and a second semiconductor layer coupled to the first semiconductor layer and having a second bandgap between a second conduction band and a second valence band, wherein the second valence band is higher than the first valence band and wherein the second semiconductor layer comprises a two dimensional hole gas and a third semiconductor layer coupled to the second semiconductor layer and having a third bandgap between a third conduction band and a third valence band, wherein the third valence band is lower than the second valence band and wherein the third semiconductor layer is coupled to the emitter.

Modulation doped super-lattice base for heterojunction bipolar transistors

Growing community of inventors

Calabasas, CA, United States of America

Tahir Hussain