Samsung Electronics Co., Ltd.

Taeyoung Song

Sung In Kim

Eun Sub Shim

Haesung Jung

Changhyun Park

Kwansik Cho

An image sensor is provided. The image sensor includes: a pixel array of pixels arranged in a row and column directions. A first pixel provided in a first row of the pixel array includes a first sub-pixel connected with a first metal line, a second sub-pixel connected with a second metal line, a third sub-pixel connected with a third metal line, and a fourth sub-pixel connected with a fourth metal line. When a read-out operation is performed on the first pixel, signals applied to the first through fourth metal lines are sequentially enabled. Based on the applied signals, at least a part of charges accumulated in the first through fourth sub-pixels is diffused to a first floating diffusion node. The first sub-pixel and the third sub-pixel are adjacent in the column direction, and the first sub-pixel and the second sub-pixel are adjacent in the row direction.

Image sensor

An image sensor includes: a first device isolation part in a substrate and defining an active region; a first gate electrode having a first and second gate sidewalls; and a first impurity region and a second impurity region adjacent to the first and second gate sidewalls, wherein the active region includes: a first active central part; a first active protrusion; and a second active protrusion, wherein the first device isolation part has a first isolation sidewall overlapping the first active central part, and wherein a first straight line is at least partially spaced apart from the first isolation sidewall, wherein the first straight line links a first point, at which the first active protrusion meets the first active central part, to a second point, at which the second active protrusion meets the first active central part.

Image sensor and semiconductor device including asymmetric active region

An image sensor may include a substrate having first and second surfaces opposite to each other and including unit pixel regions and impurity regions near the first surface, a device isolation pattern provided on the first surface to define the impurity regions, and an interconnection layer including an insulating layer covering the first surface of the substrate, interconnection lines on the insulating layer, and a penetration structure penetrating the insulating layer. The penetration structure may include a first pattern connected to one of the impurity regions and in contact with at least a portion of the device isolation pattern, a second pattern provided on the first pattern and in contact with the interconnection lines, and a third pattern provided between the first and second patterns. A top surface of the first pattern may be higher than that of the device isolation pattern.

Growing community of inventors

Hwaseong-si, South Korea

Taeyoung Song