Samsung Electronics Co., Ltd.

Taeyoung Oh

Su Yeon Doo

Jongcheol Kim

Kiheung Kim

Seungjun Shin

Hyongryol Hwang

Kyungho Lee

Kyungsoo Ha

Chulsung Park

Hohyun Shin

Hyunsung Shin

Suyeon Doo

Namjong Kim

Kyung-Soo Ha

Seungjun Bae

Hye-Ran Kim

Young-Hoon Son

Sungyong Cho

Hyeran Kim

Sihong Kim

Youngsoo Sohn

Taekwoon Kim

Jinseong Yun

Ki-Heung Kim

Youngdo Um

Hoseok Seol

Yoonjae Jeong

A method of operating a memory module that communicates with a memory controller includes: entering a one-time programmable (OTP) addressing mode based on an OTP command received from the memory controller; determining whether a guard key sequence is satisfied based on a plurality of mode register commands received from the memory controller; and programming, based on a determination that the guard key sequence is satisfied, a unique identifier (ID), corresponding to a target memory device, into the target memory device, among a plurality of memory devices included in the memory module.

Memory module for performing one-time programmable (OTP) addressing operation to store unique ID of each memory device in an ID storge region of each memory device, and storage device including the same

A method of operating a memory device includes receiving, from a memory controller, an operation command that is synchronized with a clock signal, receiving a data clock signal having a full-rate frequency and a synchronization pattern provided by at least one of a plurality of data signals. The clock signal and the data clock signal are then synchronized using a synchronization operation based on the synchronization pattern. The data clock signal may be received after a first delay time passes from a time point at which the operation command is received. The first delay time is a delay time necessary to prepare the synchronization operation.

Memory device, operation method of a memory device, and operation method of a memory controller

A semiconductor memory device, including a memory cell array; a row hammer management circuit configured to: count a number of accesses based on an active command, and based on a first command applied after the active command, perform an internal read-update-write operation to read the count data from the count cells of a target memory cell row, and to write updated count data in the count cells of the target memory cell row; and a column decoder configured to: access a first memory cell using a first bit-line; and store data in the first memory cell using a first voltage, or perform an internal write operation to store the count data in the first memory cell using a second voltage greater than the first voltage during an internal write time interval smaller than a reference write time interval.

Semiconductor memory device and memory system including the same

A semiconductor device includes an input/output interface with a first data input/output pin, a plurality of second data input/output pins, and a write clock signal pin, which is configured to receive a write clock signal from a memory controller. The first data input/output pin is configured to receive write training data from the memory controller during a write training operation, and the plurality of second data input/output pins feed result values of the write training to the memory controller. This write training is performed by the semiconductor device using the write clock signal and the write training data.

Semiconductor devices capable of performing write training without read training, and memory system including the same

A semiconductor memory device includes a memory cell array and a column access circuit. The memory cell array includes a plurality of sub-array blocks and each of the sub-array blocks includes volatile memory cells. The column access circuit receives a plurality of data units, each of which includes normal data and meta data having a ratio of k:, which is associated with managing the normal data, allocates p column selection lines associated with transferring the data units to the bit-lines to a plurality of normal data and a plurality of meta data in the data units with the ratio of k:, and stores a sub unit of a first normal data among the plurality of normal data and a sub unit of a first meta data in a first region and a second region of a first sub-array block of the plurality of sub-array blocks, respectively.

Semiconductor memory device and method for storing meta data in sub-array blocks of memory cell array

A semiconductor memory device includes a plurality of memory cells partitioned into a plurality of row blocks that are each associated with at least one respective row block identity bit within a portion of a row address. A row decoder is provided, which includes a repair controller having a plurality of fuse boxes therein that correspond to respective ones of the plurality of row blocks and include a first fuse box configured to store a first defective address. The repair controller is configured to: (i) activate a first redundancy word-line, which replaces a first defective word-line designated by the first defective address, in response to comparing a first access address with the first defective address output from the first fuse box, during a first mode, and (ii) activate a second redundancy word-line, which replaces a first edge word-line designated by the first access address, in response to comparing the first access address with a first reset address output from the first fuse box, during a second mode.

Semiconductor memory device and method of operating semiconductor memory device

A memory system that controls latency for a plurality of clock signals and outputs at least one of read data and write data includes a memory controller configured to receive a data output command from a host, generate a plurality of clock signals for outputting data, and control latency of the plurality of clock signals, and an input/output (I/O) circuit configured to output data based on the clock signals having the controlled latency.

Memory system for controlling heterogeneous clock signal delay modes, method of operating the memory system, and memory controller

A semiconductor memory device includes a memory cell array, a row hammer management circuit and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The row hammer management circuit counts the number of instances of access of each of the memory cell rows, such as in response to the receipt of an active command, to store the counted values in count cells of each of the memory cell rows as count data and, in response to a first command, initiates an internal read-update-write operation to read the count data, to update the read count data, and to write the updated count data in the count cells. The control logic circuit may performs an internal write operation to write the updated count data in the count cells during a second write time interval that is smaller than a first write time interval associated with a normal write operation.

Semiconductor memory device and methods of operation

A memory device includes: a plurality of command and address (CA) samplers configured to receive, as a plurality of first CA signals, a command comprising a predetermined pattern via a CA bus based on an exit of a sleep mode, wherein each of the plurality of CA samplers further is configured to sample a corresponding first CA signal among the plurality of first CA signals; and a command decoder configured to check a parity error in the plurality of first CA signals sampled by the plurality of CA samplers.

Memory device, memory control device and operating method of memory device for checking command and address (CA) signal with predetermined pattern of command

Provided is a memory system including a host system including a memory controller configured to control a read or write operation for a plurality of memory ranks, based on target or non-target information for the plurality of memory ranks, and a memory device including a storage configured to store on-die termination (ODT) information of the memory ranks. Here, the memory controller is further configured to determine a target rank to be read or written, and transmit information about the determined target rank, to the memory device, and the memory device is further configured to perform a comparison of the ODT information of the memory ranks stored in the storage with target or non-target information received from the memory controller, and change an ODT value of the target rank, based on target information received from the memory controller based on a result of the comparison.

Memory system for optimizing on-die termination settings of multi-ranks, method of operation of memory system, and memory controller

A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.

Semiconductor memory devices

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.

A semiconductor die includes a first pin configured to output a first on-die termination (ODT) control signal to a second semiconductor die, the second semiconductor die comprising a plurality of second ODT circuits each having an ODT that is responsive to the first ODT control signal; and a second pin configured to receive a second ODT control signal output from the second semiconductor die, the semiconductor die comprising a plurality of first ODT circuits each having an ODT that is responsive to the second ODT control signal.

Semiconductor die for controlling on-die-termination of another semiconductor die, and semiconductor devices including the same

A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.

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Seoul, South Korea

Taeyoung Oh