Samsung Electronics Co., Ltd.

Taeyong Bae

Hoonseok Seo

Euibok Lee

Provided is a semiconductor device including a a front-end-of-line (FEOL) structure and a back-end-of-line (BEOL) structure connected to the FEOL structure, wherein the FEOL structure includes at least one source/drain region and at least one gate structure, and the BEOL structure includes: a plurality of 1fine metal lines arranged in a row with a same pitch, each of the plurality of 1fine metal lines having a same width; and at least one 1wide metal line formed at a side of the plurality of 1fine metal lines, the 1wide metal line having a width greater than the width of the 1fine metal line, and wherein each of the plurality of 1fine metal lines includes a material different from a material included in the 1wide metal line.

Semiconductor device with fine metal lines for BEOL structure and method of manufacturing the same

Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a first insulating layer and a plurality of metal wires on the first insulating layer. The plurality of metal wires may include a first metal wire including a first upper surface and a first lower surface that faces the first insulating layer and a second metal wire including a second upper surface and a second lower surface that faces the first insulating layer and is coplanar with the first lower surface. The first metal wire may have a first width monotonically decreasing from the first lower surface to the first upper surface, and the second metal wire may have a second width monotonically increasing from the second lower surface to the second upper surface.

Method of forming an integrated circuit device having an etch-stop layer between metal wires

A method of manufacturing a semi-damascene structure of a semiconductor device includes: forming a 1intermetal dielectric layer; forming a 1hardmask layer and at least one 1photoresist pattern on the 1intermetal dielectric layer; patterning at least one via hole penetrating through the 1hardmask layer and the 1intermetal dielectric using the 1photoresist pattern; removing the 1photoresist pattern among the 1photoresist pattern and the 1hardmask layer; forming a metal structure in the via hole such that the metal structure fills in the vial hole and extends on the 1hardmask layer; patterning the metal structure to form at least one 1trench penetrating at least the metal structure at a portion where the metal structure extends on the 1hardmask layer; and filling the 1trench with a 2inter-metal layer.

Semi-damascene structure with dielectric hardmask layer

Provided is a semiconductor device including a front-end-of-line (FEOL) structure and a back-end-of-line (BEOL) structure connected to the FEOL structure, wherein the FEOL structure includes at least one source/drain region and at least one gate structure, and the BEOL structure includes: a plurality of 1fine metal lines arranged in a row with a same pitch, each of the plurality of 1fine metal lines having a same width; and at least one 1wide metal line formed at a side of the plurality of 1fine metal lines, the 1wide metal line having a width greater than the width of the 1fine metal line, and wherein each of the plurality of 1fine metal lines includes a material different from a material included in the 1wide metal line.

A semiconductor device structure includes: at least one inter-metal layer stacked in a vertical direction; and avia structure penetrating the at least one inter-metal layer, wherein, in the at least one inter-metal layer, avertical side of thevia structure does not contact a barrier metal pattern while avertical side of thevia structure opposite to thevertical side of thevia structure contacts the barrier metal pattern.

Growing community of inventors

Albany, NY, United States of America

Taeyong Bae