Qualcomm Incorporated

Taewoo Kwak

Joseph Dale Rutkowski

Sugato Mukherjee

Hee Jun Park

Christopher Kong Yee Chun

Techniques and apparatus for driving the gate of a high-side transistor in a switched-mode power supply (SMPS) circuit, such as an inverting buck-boost converter or a buck converter. One example technique to pull down the gate voltage of the high-side transistor involves a multi-step approach, in which the gate voltage is initially discharged to a lower voltage level, and once the gate voltage falls below a certain level, an auxiliary switch can take over to completely turn off the high-side transistor. One example SMPS circuit generally includes a high-side transistor, a pulldown gate driver having an output coupled to a gate of the high-side transistor, a pulse generator having an output coupled to an input of the pulldown gate driver, and a first switch coupled between the gate and a source of the high-side transistor.

High-side n-type power transistor gate driving techniques without a bootstrap capacitor

Techniques and apparatus for driving transistor gates of a switched-mode power supply (SMPS) circuit. One example power supply circuit generally includes a switching converter having a switching transistor and a gate driver having an output coupled to a gate of the switching transistor. The gate driver includes a first switching device coupled between the output of the gate driver and a first voltage rail; a second switching device coupled between the output of the gate driver and a voltage node of the gate driver; a third switching device coupled between the voltage node of the gate driver and a second voltage rail; and a voltage clamp coupled in series with a fourth switching device, the voltage clamp and the fourth switching device being coupled between a third voltage rail and the voltage node (or the output of the gate driver).

Gate driving technique to lower switch on-resistance in switching converter applications

Systems, methods, and computer programs are provided for controlling power in a computing device. One embodiment is a system comprising a plurality of power rails coupled to one or more computing device components. Each power rail has a primary power supply for producing current at a corresponding requested voltage. The system further comprises a shared secondary power supply selectively coupled to the plurality of power rails for providing a current increase. A controller selects one of the plurality of power rails to receive the current increase. The controller generates a control signal to electrically couple the shared secondary power supply to the selected power rail to receive the current increase.

Peak current support for a power rail system via a shared secondary power supply

Method and apparatus is disclosed for providing a controlled pre-charging current for capacitive loads coupled to a boost converter. For at least some embodiments, the boost converter may include a high-side field effect transistor (FET) and a low-side FET. The boost converter may provide the pre-charge current by periodically enabling the high-side FET while the low-side FET is maintained in an off state. The high-side FET may be enabled by a square-wave signal. The pre-charge current may be delivered until the output voltage of the boost converter exceeds a reference voltage. After the output voltage exceeds the reference voltage, the boost converter may transition to a normal (switching) operation.

Boost converter with pre-charge current

Techniques for improving the transient response in a switching converter are provided. An example of a gate driving circuit for driving a high-side switch in a switching converter according to the disclosure includes a first switch operably coupled to a source lead and a gate lead of the high-side switch, a first super source follower circuit operably coupled to the gate lead of the high-side switch, and a mid-voltage power supply operably coupled to the first super source follower circuit.

Fast transient high-side gate driving circuit

A loop compensation circuit includes a differential difference amplifier having a first transconductance stage with a first input terminal and a second input terminal. The first input terminal is coupled to a voltage reference and the second input terminal is coupled to a feedback node. The amplifier also includes a second transconductance stage having a third input terminal and a fourth input terminal. The third input terminal is coupled to a virtually specified fixed voltage and the fourth input terminal is coupled to a fixed specified voltage. The loop compensation circuit also includes a feedback impedance coupled between an output of the differential difference amplifier and the third input terminal and a second impedance between the third input terminal and the fixed specified voltage.

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San Diego, CA, United States of America

Taewoo Kwak