Stats Chippac Pte. Ltd.

Samsung Electronics Co., Ltd.

Taewoo Kang

Il Kwon Shim

Jong-Woo Ha

Byung Lyul Park

KyungOe Kim

Ki Youn Jang

DongSoo Moon

Hyungjun Jeon

Kyoung Hwan Kim

Haengcheol Choi

Rajendra D Pendse

Jaewon Choi

Yong Hee Kang

HyunSu Shin

Seong Bo Shim

Sungbum Kim

A semiconductor package may include a lower package including a first substrate, a first semiconductor chip on the first substrate, and a first molding portion on the first substrate to cover the first semiconductor chip, an interposer substrate on the first semiconductor chip, a supporting portion between the interposer substrate and the first substrate to support the interposer substrate, a connection terminal connecting the interposer substrate to the first substrate, and an upper package on the interposer substrate. The upper package may include a second substrate, a second semiconductor chip on the second substrate, and a second molding portion on the second substrate to cover the second semiconductor chip.

Semiconductor packages including at least one supporting portion

A substrate processing apparatus may include a substrate jig device and a transfer unit, which is configured to hold a substrate in a non-contact state and move the substrate toward the substrate jig device. The substrate jig device may include a supporter, which is configured to support an edge of the substrate and have an opening, a first suction part, which overlaps with a center region of the opening and is configured to move in a first direction, and a plurality of second suction parts, which overlap with an edge region of the opening and are configured to move toward the opening. Here, the first direction may be a direction passing through the opening.

Substrate processing apparatus and method of manufacture using the same

A method of manufacturing a semiconductor package includes forming a preliminary package, on a supporting substrate, which includes a connection substrate, a semiconductor chip and a molding pattern on the connection substrate and the semiconductor chip, forming a buffer pattern on the molding pattern, and forming a carrier substrate, on the buffer pattern, which includes a first portion contacting the buffer pattern and a second portion contacting the molding pattern.

Method of manufacturing semiconductor package

A stackable integrated circuit package system including mounting an integrated circuit device over a package carrier, mounting a stiffener over the package carrier and mounting a mountable package carrier over the stiffener with a vertical gap between the integrated circuit device and the mountable package carrier.

Stackable integrated circuit package system

An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.

Electronic system with expansion feature

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed; and attaching a base substrate connector to the base substrate directly below the leadframe pillar.

Integrated circuit packaging system with lead frame and method of manufacture thereof

An integrated circuit package system comprising: providing a package substrate; attaching an integrated circuit over the package substrate; and attaching a side substrate adjacent the integrated circuit over the package substrate.

Integrated circuit package system with side substrate having a top layer

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; and removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed.

A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.

Growing community of inventors

Suwon-si, South Korea

Taewoo Kang