Samsung Electronics Co., Ltd.

Taesung Lee

Jeongdon Ihm

Seonkyoo Lee

Byunghoon Jeong

Anil Kavala

Jangwoo Lee

Seungjun Bae

Dong-Su Jang

Kyoungtae Kang

Junghwan Choi

Jongseok Lee

Tongsung Kim

Soon Suk Hwang

Chulseung Lee

Daehoon Na

Choongeui Lee

Uihyoung Lee

Jaewoo Im

Honyun Park

Jiwan Jung

Sewan Kim

Younggyu Lee

A semiconductor memory device may include an impedance adjustment pad, a dummy pull-down driver and an external resistor connected in parallel between the impedance adjustment pad and a ground, a recursive code generation circuit configured to recursively generate a pull-up code and a pull-down code corresponding to a target resistance by using the external resistor and the dummy pull-down driver as a reference resistance, in an impedance calibration operation of the semiconductor memory device, a code register configured to store the generated pull-up code and the pull-down code, and a calibration control logic circuit configured to control the recursive code generation circuit during a plurality of steps in the impedance calibration operation while adjusting a resistance value of the dummy pull-down driver.

Semiconductor memory device performing recursive ZQ calibration and calibration method thereof

An equalizer includes a first pulse width controller that is configured to generate a first signal by increasing a first pulse width of a first data signal having a first logic level, the first data signal corresponding to a current data bit, a second pulse width controller that is configured to generate a second signal by increasing a second pulse width of the first data signal having a second logic level, a first sampler that is configured to generate a first sampled signal by sampling the first signal, a second sampler that is configured to generate a second sampled signal by sampling the second signal, and a multiplexer that is configured to output the first sampled signal or the second sampled signal based on a value of a previous data bit.

Equalizer for removing inter symbol interference of data signal by increasing pulse widths of logic low level and logic high level of data signal

A method of fabricating a semiconductor device includes forming a dielectric layer on a lower structure. The method includes forming an opening to penetrate through the dielectric layer. The method includes alternately repeating a first operation, in which a first sputtering deposition process is performed to form a first metal pattern in the opening, and a second operation, in which a second sputtering deposition process is performed to form a second metal pattern in the opening, two or more times to form a first metal layer. The method includes forming a second metal layer on the first metal layer in an electroplating manner, and planarizing the first and second metal layers. Moreover, first and second process times, during which the first sputtering deposition process and the second sputtering deposition process, respectively, are performed, are each about five seconds or less.

Methods of fabricating semiconductor devices

A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

Semiconductor device including delay compensation circuit

A semiconductor memory module includes data buffers that exchange first data signals with an external device, nonvolatile memory devices that are respectively connected to the data buffers through data lines, and a controller connected to the data lines. The controller receives an address, a command, and a control signal from the external device, and depending on the address, the command, and the control signal, the controller controls the data buffers through first control lines and controls the nonvolatile memory devices through second control lines.

Semiconductor memory module including nonvolatile memory devices

A semiconductor memory device may include banks. A sensor is disposed adjacent to the banks and configured to sense a temperature. An address buffer is configured to receive an address from an external device. A first demultiplexer is configured to transfer a row address in the address to one of the banks. A second demultiplexer is configured to transfer a column address in the address to one of the banks. A command buffer is configured to receive a command from the external device. A control logic block is configured to control the first and second demultiplexers and the banks in accordance with the command and bank information in the address. A data buffer is configured to exchange data signals between the banks and the external device. The control logic block may be further configured to transfer information on the temperature to the external device.

Semiconductor memory device, semiconductor memory module, and method of accessing nonvolatile memory

A data training method of a storage device, which includes a storage controller and a nonvolatile memory device, includes transmitting a read training command to the nonvolatile memory device, receiving a first training pattern output from the nonvolatile memory device in response to the read training command, receiving a second training pattern output from the nonvolatile memory device in response to the read training command, comparing the received first training pattern and the received second training pattern with a reference pattern, and determining a read timing offset of the storage controller depending on the comparison result.

Data training method of storage device

A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal.

Method of shaping a strobe signal, a data storage system and strobe signal shaping device

A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.

Nonvolatile memory device and storage device having the same

A semiconductor device of the inventive concept includes a timing circuit configured to receive a first timing signal of a first pulse width from an external device and output a second timing signal having a pulse width which is gradually being reduced from a second pulse width longer than the pulse width of the first timing signal, and a data input/output circuit receiving the second timing signal and outputting data to the external device in synchronization with the second timing signal.

Semiconductor memory system, semiconductor memory device and method of operating the semiconductor memory device

An output circuit of a nonvolatile memory device includes a sense amplification circuit configured to, during a sensing operation, generate output data based on a comparison between a first voltage on a data line and a reference voltage on a reference data line during a sensing operation, the first voltage corresponding to data read from at least one memory cell, and the sense amplification circuit being further configured to connect the reference data line with a ground terminal during the sensing operation.

Sense amplification circuits, output circuits, nonvolatile memory devices, memory systems, memory cards having the same, and data outputting methods thereof

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Hwaseong-si, South Korea

Taesung Lee