Samsung Electronics Co., Ltd.

Yonsei University

Taemin Choi

Seongook Jung

Keonhee Cho

Taehyun Kim

Sangjin Kim

Chanho Lee

Yigwon Kim

Heekyung Choi

Yongchul Jeong

Junghak Song

Jinhee Jang

Juchang Lee

A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.

Memory device using a plurality of supply voltages and operating method thereof

A method of forming a pattern includes forming an etching object layer on a substrate. A photoresist layer including a metal, oxygen and an organic material is formed on the etching object layer. An exposure process is performed on the photoresist layer. A developing process is performed on the photoresist layer to form a photoresist pattern including a metal oxide. Ozone is provided onto the substrate to remove a residue of the photoresist layer that includes the organic material. The etching object layer is etched using the photoresist pattern as an etching mask.

Method of forming a pattern

An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first columns and including a plurality of word line assist cells in at least one second column; a plurality of word lines respectively extending on a plurality of first rows of the cell array and connected to the plurality of memory cells and the plurality of word line assist cells; and a row driver configured to drive the plurality of word lines.

Integrated circuit including cell array with word line assist cells

An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first rows and a plurality of write assistance cells in at least one second row; a plurality of word lines respectively extending on the plurality of first rows; at least one write assistance line respectively extending on the at least one second row; and a row driver connected to the plurality of word lines and the at least one write assistance line, the row driver being configured to, during a write operation, activate at least one of the plurality of write assistance cells through the at least one write assistance line, wherein each of the plurality of write assistance cells includes the same transistor configuration as each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.

Integrated circuit including cell array with write assist cell

An integrated circuit memory device includes a static random access memory (SRAM) cell, and a charge storing circuit electrically coupled to the SRAM cell. A switching controller is provided, which is electrically coupled to the charge storing circuit. The switching controller and the charge storing circuit are collectively configured to save power by recycling charge associated with a bit line electrically coupled to the SRAM cell by: (i) transferring charge from the bit line to a charge storage node electrically coupled to source terminals of a pair of NMOS pull-down transistors within the SRAM cell upon commencement of a SRAM cell write operation, and then (ii) returning at least a portion of the charge to the bit line upon completion of the SRAM cell write operation.

Static random access memory (SRAM) devices and methods of operating the same

A memory device having fault detection functionality for improving functional safety and a control system including the memory device are provided. The memory device includes a first memory cell array configured to store input data and output the input data as output data and a second memory cell array configured to store bit values of a row address and a column address of the first memory cell array in which the input data is stored, and output the bit values of the row address and the column address as an internal row address and an internal column address. The row/column address designating a read operation may be compared to the internal row/column address, and an address comparison signal as a result of the comparison may be output. The address comparison signal may provide fault detection functionality for a data error of an automotive electronic system.

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Seoul, South Korea

Taemin Choi